Semiconductor device and method for manufacturing the same

• US 10,522,692 B2
• Filed: 05/05/2016
• Issued: 12/31/2019
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US15/147,069
• Publication Number:
  US 20160247939A1
• Time in Patent Office: 1,335 Days
• Field of Search: 257 43, 257 52, 257E29095, 257E33004, 257E29101, 257E2908, 257E29083, 257E31047
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.

Claims

1. A semiconductor device comprising:

a transistor comprising;

an oxide semiconductor film comprising;

a first region;

a pair of second regions, the first region located between the pair of second regions; and

a pair of third regions, the first region and the pair of second regions located between the pair of third regions;

a gate insulating film over the oxide semiconductor film;

a gate electrode over the gate insulating film and overlapping with the first region;

a first electrode electrically connected to the oxide semiconductor film; and

a second electrode electrically connected to the oxide semiconductor film,

wherein the oxide semiconductor film comprises indium, gallium and zinc,

wherein the gate electrode, the first electrode, and the second electrode comprise copper,

wherein the gate insulating film comprises a fourth region overlapping with the first region and comprises a pair of fifth regions overlapping with at least a part of the pair of second regions,

wherein the gate insulating film comprising the fourth region and the pair of fifth regions is one insulating film,

wherein the gate insulating film is not in contact with a side surface of the gate electrode, and

wherein a conductivity of the pair of third regions is higher than a conductivity of the pair of second regions.

2. The semiconductor device according to claim 1,

wherein the first electrode is in contact with a top surface of the one of the pair of third regions, and

wherein the second electrode is in contact with a top surface of the other of the pair of third regions.

3. The semiconductor device according to claim 1,

wherein the gate insulating film is an oxide insulating film.

4. The semiconductor device according to claim 1,

wherein the transistor is n-channel transistor.

5. A semiconductor device comprising:

a transistor comprising;

an oxide semiconductor film comprising;

a first region;

a pair of second regions, the first region located between the pair of second regions; and

a pair of third regions, the first region and the pair of second regions located between the pair of third regions;

a gate insulating film over the oxide semiconductor film;

a gate electrode over the gate insulating film and overlapping with the first region;

a first electrode electrically connected to the oxide semiconductor film; and

a second electrode electrically connected to the oxide semiconductor film,

wherein the oxide semiconductor film comprises indium, gallium and zinc,

wherein the gate electrode, the first electrode, and the second electrode comprise copper,

wherein the gate insulating film comprises a fourth region overlapping with the first region and comprises a pair of fifth regions overlapping with at least a part of the pair of second regions,

wherein the gate insulating film comprising the fourth region and the pair of fifth regions is one insulating film,

wherein the gate insulating film is not in contact with a side surface of the gate electrode, and

wherein a carrier density of the pair of third regions is higher than a carrier density of the pair of second regions.

6. The semiconductor device according to claim 5,

wherein the first electrode is in contact with a top surface of the one of the pair of third regions, and

wherein the second electrode is in contact with a top surface of the other of the pair of third regions.

7. The semiconductor device according to claim 5,

wherein the gate insulating film is an oxide insulating film.

8. The semiconductor device according to claim 5,

wherein the transistor is n-channel transistor.