Methods of manufacturing semiconductor device

• US 10,522,694 B2
• Filed: 09/28/2017
• Issued: 12/31/2019
• Est. Priority Date: 12/15/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, I-Sheng, Huang, Szu-Wei, Chiang, Hung-Li, Wu, Cheng-Hsien, Yeh, Chih Chieh
• Primary Examiner(s): Slutsker, Julia
• Application Number:
  US15/719,121
• Publication Number:
  US 20180175214A1
• Time in Patent Office: 824 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a multi-layer structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate;

patterning the multi-layer structure into a fin structure;

forming a sacrificial gate structure over the fin structure, the sacrificial gate structure covering a first part of the fin structure including a channel region and leaving a second part of the fin structure including source and drain regions exposed;

forming source and drain epitaxial layers that wrap around the fin structure in the source and drain regions to form epitaxial source and drain structures, wherein each one of the source and drain epitaxial layers is a physically connected segment;

removing the sacrificial gate structure to expose the channel region;

removing the second semiconductor layers in the channel region thereby exposing the first semiconductor layers in the channel region to form spaced apart core layers in the in the channel region;

forming one or more semiconductor shell layers at least partially around the core layers in the channel region to form multilayer semiconductor wires, each of the multilayer semiconductor wires comprising a core layer at least partially wrapped around with the one or more semiconductor shell layers; and

forming a gate dielectric layer and a gate electrode layer around the multilayer semiconductor wires in the channel region.

2. The method of claim 1, wherein the first semiconductor layers comprise Si or a Si-based compound, and wherein the second semiconductor layers comprise SiGe having a different composition than the first semiconductor layers.

3. The method of claim 1, wherein the core layer comprises a Si_1-xGe_x semiconductor and each of the multilayer semiconductor wires comprises a first shell made of a Ge epitaxial layer covering the core layer and a second shell made of a Si epitaxial layer covering the first shell.

4. The method of claim 1, wherein the epitaxial source and drain structures include at least one of SiP, SiCP and SiC.

5. The method of claim 1, wherein the core layer comprises a Si_1-xGe_x semiconductor and each of the multilayer semiconductor wires comprises a first shell made of a Si epitaxial layer covering the core layer and a second shell made of a Ge epitaxial layer covering the first shell, and wherein the epitaxial source and drain structures include at least one of SiP, SiCP and SiC.

6. The method of claim 5, wherein the core layer comprises a cylinder with a substantially circular cross section and the first and second shells comprise cylindrical shells having substantially circular cross sections, and wherein the epitaxial source and drain structures include SiGe or Ge.

7. The method of claim 5, wherein a thickness of the core layer is within a range of about 2-4 nm, and wherein a thickness of the first or the second shell is within a range of about 1-2 nm.

8. The method of claim 5, wherein, one of the first shell or the second shell has a tensile stress and a lower conduction-band edge energy (E_C), and wherein another one of the first shell or the second shell has a compressive stress and a higher valence-band edge energy (E_V).

9. A method of manufacturing a semiconductor device, comprising:

forming a multi-layer structure in a first direction over a substrate, the multi-layer structure including first semiconductor layers and second semiconductor layers alternately stacked over one another;

patterning the multi-layer structure into a plurality of fin structures;

forming a sacrificial gate structure over the plurality of fin structures, the sacrificial gate structure covering a first part of the plurality of fin structures that comprises a channel region, while leaving a second part of the plurality of fin structures that comprises source and drain regions exposed;

forming source and drain epitaxial layers that wrap around the plurality of fin structures in the source and drain regions to form epitaxial source and drain structures, wherein each one of the source and drain epitaxial layers is a physically connected segment;

removing the sacrificial gate structure to expose the channel regions of the plurality of fin structures;

removing the second semiconductor layers in the channel regions of the plurality of fin structures, thereby exposing first semiconductor layers in the channel regions of the plurality of fin structures to form spaced apart core layers in the channel regions of the plurality of fin structure;

rounding the spaced apart core layers in the channel regions;

forming one or more semiconductor shell layers at least partially around the rounded core layers in the channel regions to form multilayer semiconductor wires, each of the multilayer semiconductor wires comprising a core layer at least partially wrapped around with the one or more semiconductor shell layers; and

forming a gate dielectric layer and a gate electrode layer around the multilayer semiconductor wires in the channel regions of the plurality of fin structures,

wherein a first shell layer of the one or more semiconductor shell layers is connected to an adjacent first shell layer corresponding to a neighboring multilayer semiconductor wire.

10. The method of claim 9, further comprising:

removing the second semiconductor layers in the channel regions of the plurality of fin structures before the epitaxial source and drain structures to prevent the gate electrode layer from contacting the source and drain epitaxial layers.

11. The method of claim 9, wherein the core layer comprise a Si_1-xGe_x semiconductor and the one or more semiconductor shells comprises a first shell made of a Ge epitaxial layer covering the core layer and a second shell made of a Si epitaxial layer covering the first shell.

12. The method of claim 9, wherein the epitaxial source and drain structures include at least one of SiP, SiCP and SiC.

13. The method of claim 11, wherein the core layer comprises a cylindrical core having a substantially circular cross section and the first and second shells comprise cylindrical shells having substantially circular cross sections, and wherein the epitaxial source and drain structures include SiGe or Ge.

14. The method of claim 11, wherein, a thickness of the core layer is within a range of about 2-4 nm, and wherein a thickness of the first or the second shell is within a range of about 1-2 nm.

15. The method of claim 11, wherein one of the first shell or the second shell has a tensile stress and a lower conduction-band edge energy (E_C), and wherein another one of the first shell or the second shell has a compressive stress and a higher valence-band edge energy (E_V).

16. The method of claim 9, wherein the first semiconductor layers comprise Si or a Si-based compound, and wherein the second semiconductor layers comprise SiGe.

17. A method of manufacturing a semiconductor device, comprising:

forming a multi-layer structure in a first direction over a substrate, the multi-layer structure including first semiconductor layers and second semiconductor layers alternately stacked over one another;

patterning the multi-layer structure into a plurality of fin structures;

forming a sacrificial gate structure over the plurality of fin structures, the sacrificial gate structure covering a first part of the plurality of fin structures that comprises a channel region, while leaving a second part of the plurality of fin structures that comprises source and drain regions exposed;

forming source and drain epitaxial layers that wrap around the plurality of fin structures in the source and drain regions to form epitaxial source and drain structures, wherein each one of the source and drain epitaxial layers is a physically connected segment;

removing the sacrificial gate structure to expose the channel regions of the plurality of fin structures;

removing the second semiconductor layers in the channel regions of the plurality of fin structures, thereby exposing first semiconductor layers in the channel regions of the plurality of fin structures to form spaced apart core layers in the channel regions of the plurality of fin structure;

rounding the spaced apart core layers in the channel regions;

forming one or more semiconductor shell layers at least partially around the rounded core layers in the channel regions to form multilayer semiconductor wires, each of the multilayer semiconductor wires comprising a core layer at least partially wrapped around with the one or more semiconductor shell layers;

forming a gate dielectric layer and a gate electrode layer around the multilayer semiconductor wires in the channel regions of the plurality of fin structures, wherein a first shell layer of the one or more semiconductor shell layers is connected to an adjacent first shell layer corresponding to a neighboring multilayer semiconductor wire;

forming an interlayer dielectric layer covering the plurality of fin structure; and

removing parts of the interlayer dielectric layer to create a plurality of openings, the plurality of opening extending from topmost part of the interlayer dielectric layer to a gate metal and the source and drain regions, wherein contact metals reach the gate metal and the source and drain regions through the plurality of openings.

18. The method of claim 17, wherein the core layer comprise a Si_1-xGe_x semiconductor and the one or more semiconductor shells comprises a first shell made of a Ge epitaxial layer covering the core layer and a second shell made of a Si epitaxial layer covering the first shell.

19. The method of claim 17, wherein the epitaxial source and drain structures include at least one of SiP, SiCP and SiC.

20. The method of claim 17, wherein the core layer comprises a cylindrical core having a substantially circular cross section and the first and second shells comprise cylindrical shells having substantially circular cross sections, and wherein the epitaxial source and drain structures include SiGe or Ge.