Under-cut via electrode for sub 60nm etchless MRAM devices by decoupling the via etch process

• US 10,522,741 B1
• Filed: 06/14/2018
• Issued: 12/31/2019
• Est. Priority Date: 06/14/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Yi, Shen, Dongna, Wang, Yu-Jen
• Primary Examiner(s): Ho, Tu-Tu V
• Application Number:
  US16/008,650
• Publication Number:
  US 20190386201A1
• Time in Patent Office: 565 Days
• Field of Search: 257421
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: H01F 41/308 lift-off processes, e.g. ion milling, for trimming or patterning
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Claims

1. A method for fabricating a magnetic tunneling junction (MTJ) structure, the method comprising:

depositing a first dielectric layer on a bottom electrode;

partially etching through the first dielectric layer using a photoresist pattern to form a first via opening having straight sidewalls;

removing the photoresist pattern and etching all the way through the first dielectric layer to the bottom electrode in the first via opening to form a second via opening, wherein the second via opening has tapered sidewalls;

depositing a metal layer over the first dielectric layer and in the second via opening and thereafter removing the metal layer overlying the first dielectric layer;

removing remaining portions of the first dielectric layer, wherein the metal-filled second via opening forms an electrode plug on the bottom electrode;

depositing MTJ stacks on the electrode plug and on the bottom electrode, wherein the MTJ stacks are discontinuous;

depositing a second dielectric layer over the MTJ stacks;

polishing the second dielectric layer to expose a top surface of the MTJ stack on the electrode plug; and

depositing a top electrode layer on the second dielectric layer and contacting the top surface of the MTJ stack on the electrode plug.

2. The method according to claim 1, wherein the first dielectric layer comprises SiO₂, SiN, SiON, SiC, SiCN, or carbon having a thickness greater than or equal to 100 nanometers.

3. The method according to claim 1, further comprising:

prior to partially etching through the first dielectric layer, depositing a bottom anti-reflective coating (BARC) comprising a cross-linked polymer or a dielectric anti-reflective coating (DARC) on the first dielectric layer;

spin-coating a photoresist on the BARC layer; and

patterning the photoresist to form the photoresist pattern having an opening with a width between about 70 nm and about 80 nm.

4. The method according to claim 1, wherein partially etching through the first dielectric layer comprises a fluorine carbon-based plasma alone, or mixed with an argon- or nitrogen-containing fluid, or a physical etch.

5. The method according to claim 1, wherein the tapered via has a bottom width of about 40 to 50 nanometers, a top width of about 60 to 80 nanometers, and a taper angle between about 10 and 80 degrees.

6. The method according to claim 1, wherein the metal layer comprises Ta, Ti, TaN, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys.

7. The method according to claim 1, wherein removing the metal overlying the first dielectric layer comprises chemical mechanical polishing.

8. The method according to claim 1, wherein removing remaining portions of the first dielectric layer comprises etching with:

fluorine carbon if the first dielectric layer comprises SiO₂ or SiON;

CH₂F₂ if the first dielectric layer comprises SiN or SiCN; and

O₂ if the first dielectric layer comprises carbon; and

wherein a bias power of less than or equal to 100 Watts and a source power of greater than or equal to 200 Watts is used.

9. The method according to claim 1, further comprising using IBE trimming at an angle of between about 60 and 80 degrees to proportionally decrease the via electrode'"'"'s top and bottom sizes subsequent to removing remaining portions of the first dielectric layer.

10. The method according to claim 1, wherein the electrode plug has a top width of less than or equal to 60 nanometers and a bottom width of less than or equal to 40 nanometers.

11. A method for fabricating a magnetic tunneling junction (MTJ) structure, the method comprising:

depositing a first dielectric layer on a bottom electrode;

partially etching through the first dielectric layer using a photoresist pattern to form a first via opening having straight sidewalls;

thereafter removing the photoresist pattern and etching all the way through the first dielectric layer to the bottom electrode in the first via opening to form a second via opening, wherein the second via opening has tapered sidewalls;

depositing a metal layer over the first dielectric layer and in the second via opening and thereafter removing the metal layer overlying the first dielectric layer;

removing portions of the first dielectric layer adjacent to the metal in the second via opening, wherein the metal in the second via opening forms an electrode plug on the bottom electrode;

thereafter IBE trimming the electrode plug to proportionally decrease a top width and a bottom width of the via electrode to less than or equal to 60 nanometers and a less than or equal to 40 nanometers, respectively;

thereafter depositing MTJ stacks on the electrode plug and on the bottom electrode, wherein the MTJ stacks are discontinuous;

depositing a second dielectric layer over the MTJ stacks;

polishing the second dielectric layer to expose a top surface of the MTJ stack on the electrode plug; and

thereafter depositing a top electrode layer on the second dielectric layer and contacting the top surface of the MTJ stack on the electrode plug.

12. The method according to claim 11, wherein the first dielectric layer comprises SiO₂, SiN, SiON, SiC, SiCN, or carbon having a thickness greater than or equal to 100 nanometers.

13. The method according to claim 11, further comprising:

prior to partially etching through the first dielectric layer, depositing a bottom anti-reflective coating (BARC) comprising a cross-linked polymer or a dielectric anti-reflective coating (DARC) having a thickness between 30 nanometers and 100 nanometers on the first dielectric layer;

spin-coating a photoresist on the BARC layer; and

patterning the photoresist to form the photoresist pattern having an opening with a width between about 70 nm and about 80 nm.

14. The method according to claim 11, wherein partially etching through the first dielectric layer comprises a fluorine carbon-based plasma alone, or mixed with an argon- or nitrogen-containing fluid, or a physical etch.

15. The method according to claim 11, wherein the tapered via has a bottom width of about 40 to 50 nanometers, a top width of about 60 to 80 nanometers, and a taper angle between about 10 and 80 degrees.

16. The method according to claim 11, wherein the metal layer comprises Ta, Ti, TaN, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys.

17. The method according to claim 11, wherein removing the metal overlying the first dielectric layer comprises chemical mechanical polishing.

18. The method according to claim 11, wherein removing portions of the first dielectric layer adjacent to the metal in the second via opening comprises etching with:

fluorine carbon if the first dielectric layer comprises SiO₂ or SiON;

CH₂F₂ if the first dielectric layer comprises SiN or SiCN; and

O₂ if the first dielectric layer comprises carbon; and

wherein a bias power of less than or equal to 100 Watts and a source power of greater than or equal to 200 Watts is used.

19. The method according to claim 11, wherein the IBE trimming is performed at an angle of between about 60 and 80 degrees.

20. The method according to claim 11, wherein removing portions of the first dielectric layer adjacent to the metal in the second via opening comprises etching the electrode plug at an etch rate of between 50 nanometers per minute and 100 nanometers per minute.