Mixed style bias network for RF switch FET stacks

• US 10,523,195 B1
• Filed: 08/02/2018
• Issued: 12/31/2019
• Est. Priority Date: 08/02/2018
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Luo, Yuan, Allison, Matt, Shapiro, Eric S.
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US16/053,710
• Time in Patent Office: 516 Days
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Embodiments include a switch stack comprising ACS FETs and mixed-style gate resistor bias networks that mitigate the effects of high leakage current. By carefully selecting the number of ACS FETs in a sub-stack that uses a rung gate resistor bias network versus a sub-stack that uses a rail gate resistor bias network, as well as by selecting particularly useful values for the gate resistors in each bias network, a tradeoff can be achieved between adverse Vg offset and Q factor. The switch stack may be configured with rung-rail gate resistor bias networks, or with rung-rail-rung gate resistor bias networks. Other embodiments include mixed-style body resistor bias networks in switch stacks comprising non-ACS FETs. Some embodiments include one or more positive-logic FETs M1-Mn, series-coupled on at least one end to an “end-cap” FET M₀ of a type that turns OFF when the applied V_GS is essentially zero volts.

Claims

1. A FET switch stack, including:

(a) a first sub-stack including;

(1) one or more series-connected ACS FETs, each ACS FET having a gate terminal; and

(2) a rung gate resistor bias network comprising gate resistors each coupled to a first control voltage and to the gate terminal of a corresponding one of the ACS FETs of the first sub-stack;

(b) a second sub-stack, series connected to the first sub-stack, including;

(1) two or more series-connected ACS FETs, each ACS FET having a gate terminal; and

(2) a rail gate resistor bias network comprising series gate resistors each coupled, directly or indirectly, to a second control voltage and to the respective gate terminals of at least two of the ACS FETs of the second sub-stack.

2. The invention of claim 1, wherein at least one ACS FET of the FET switch stack is a positive-logic FET, the FET switch stack further including at least one end-cap FET of a type that turns OFF when the V_GS of such end-cap FET is essentially zero volts.

3. The invention of claim 2, wherein each end-cap FET functions as a DC blocking capacitor when in an OFF state, and as a resistive signal path when in an ON state.

4. The invention of claim 1, wherein the series gate resistors have resistance values that are tapered from a first ACS FET of the second sub-stack to a last ACS FET of the second sub-stack.

5. The invention of claim 1, wherein the FETs of the first and second sub-stacks are placed in any physical ordering, so long as at least one parallel gate resistor and/or at least one series gate resistor separates the gate terminal of each FET from the gate terminal of any other FET.

6. A FET switch stack including:

(a) a first sub-stack including;

(1) one or more series-connected ACS FETs, each ACS FET having a gate terminal; and

(2) a rung gate resistor bias network comprising gate resistors each coupled to a first control voltage and to the gate terminal of a corresponding one of the ACS FETs of the first sub-stack;

(b) a second sub-stack, series connected to the first sub-stack, including;

(1) two or more series-connected ACS FETs, each ACS FET having a gate terminal; and

(2) a rail gate resistor bias network comprising series gate resistors each coupled, directly or indirectly, to a second control voltage and to the respective gate terminals of at least two of the ACS FETs of the second sub-stack; and

(c) a third sub-stack, series connected to the second sub-stack, including;

(1) one or more series-connected ACS FETs, each ACS FET having a gate terminal; and

(2) a rung gate resistor bias network comprising gate resistors each coupled to a third control voltage and to the gate terminal of a corresponding one of the ACS FETs of the third sub-stack.

7. The invention of claim 6, wherein at least one ACS FET of the FET switch stack is a positive-logic FET, the FET switch stack further including at least one end-cap FET of a type that turns OFF when the V_GS of such end-cap FET is essentially zero volts.

8. The invention of claim 7, wherein each end-cap FET functions as a DC blocking capacitor when in an OFF state, and as a resistive signal path when in an ON state.

9. The invention of claim 6, wherein the ACS FETs of the second sub-stack include two end ACS FETs, and the series gate resistors have resistance values that are tapered from the two end ACS FETs of the second sub-stack to a node between the two end ACS FETs of the second sub-stack.

10. The invention of claim 6, wherein the FETs of the first, second, and third sub-stacks are placed in any physical ordering, so long as at least one parallel gate resistor and/or at least one series gate resistor separates the gate terminal of each FET from the gate terminal of any other FET.

11. A FET switch stack, including:

(a) a first sub-stack including;

(1) one or more series-connected FETs, each FET having a body; and

(2) a rung body resistor bias network comprising body resistors each coupled to a first control voltage and to the body of a corresponding one of the FETs of the first sub-stack;

(b) a second sub-stack, series connected to the first sub-stack, including;

(1) two or more series-connected FETs, each FET having a body; and

(2) a rail body resistor bias network comprising series body resistors each coupled, directly or indirectly, to a second control voltage and to the respective bodies of at least two of the FETs of the second sub-stack.

12. The invention of claim 11, wherein one or more of the FETs is an ACS FET.

13. The invention of claim 11, wherein the FETs of the first and second sub-stacks are placed in any physical ordering, so long as at least one parallel body resistor and/or at least one series body resistor separates the body of each FET from the body of any other FET.

14. A FET switch stack, including:

(a) a first sub-stack including;

(1) one or more series-connected FETs, each FET having a body; and

(2) a rung body resistor bias network comprising body resistors each coupled to a first control voltage and to the body of a corresponding one of the FETs of the first sub-stack;

(b) a second sub-stack, series connected to the first sub-stack, including;

(1) two or more series-connected FETs, each FET having a body; and

(2) a rail body resistor bias network comprising series body resistors each coupled, directly or indirectly, to a second control voltage and to the respective bodies of at least two of the FETs of the second sub-stack; and

(c) a third sub-stack, series connected to the second sub-stack, including;

(1) one or more series-connected FETs, each FET having a body; and

(2) a rung body resistor bias network comprising body resistors each coupled to a third control voltage and to the body of a corresponding one of the FETs of the third sub-stack.

15. The invention of claim 14, wherein one or more of the FETs is an ACS FET.

16. The invention of claim 14, wherein the FETs of the first, second, and third sub-stacks are placed in any physical ordering, so long as at least one parallel body resistor and/or at least one series body resistor separates the body of each FET from the body of any other FET.