Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells

• US 10,523,210 B2
• Filed: 01/30/2019
• Issued: 12/31/2019
• Est. Priority Date: 02/01/2018
• Status: Active Grant

• Current Assignee: Icometrue Company Ltd.
• Original Assignee: Icometrue Company Ltd.
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Crawford, Jason
• Application Number:
  US16/262,875
• Publication Number:
  US 20190238135A1
• Time in Patent Office: 335 Days
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 14/0081 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/83104 : by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/92225 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1443 : Non-volatile random-access memory [NVRAM]
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/1737 : using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 : Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 : for memories
• CPC Class Codes: H03K 19/20 : characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 19/21 : EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element
• CPC Class Codes: H10B 10/15 : comprising a resistor load element
• CPC Class Codes: H10B 61/00 : Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/10 : comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/00 : Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/20 : comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/22 : of the metal-insulator-metal type
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 : Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 : Electrodes
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

Claims

1. A multi-chip package comprising:

a semiconductor integrated-circuit (IC) chip comprising;

a plurality of non-volatile memory cells; and

a programmable logic circuit configured to be programmed to perform a logic function, comprising a plurality of input points for an input data set for the logic operation, a multiplexer configured to select, in accordance with the input data set, a resulting value from a plurality of resulting values of a look-up table (LUT) as an output data for the logic operation, and an output point for the output data for the logic operation; and

a memory chip coupling to the semiconductor integrated-circuit (IC) chip, wherein communication between the semiconductor integrated-circuit (IC) chip and the memory chip has a data bit width greater than or equal to 64.

2. The multi-chip package of claim 1, wherein each of the plurality of non-volatile memory cells comprises a resistive-random-access-memory (RRAM) cell configured to store data associated with one of the plurality of resulting values.

3. The multi-chip package of claim 1, wherein each of the plurality of non-volatile memory cells comprises a magnetoresistive-random-access-memory (MRAM) cell configured to store data associated with one of the plurality of resulting values.

4. The multi-chip package of claim 1, wherein the programmable logic circuit comprises a plurality of static-random-access-memory (SRAM) cells configured to store the plurality of resulting values associated with data stored in the plurality of non-volatile memory cells.

5. The multi-chip package of claim 4, wherein the semiconductor integrated-circuit (IC) chip further comprises a sense amplifier configured to sense and amplify information associated with the data stored in one of the non-volatile memory cells as output data of the sense amplifier, wherein the output data of the sense amplifier is configured to be associated with one of the plurality of resulting values stored in one of the plurality of static-random-access-memory (SRAM) cells.

6. The multi-chip package of claim 4, wherein each of the plurality of non-volatile memory cells comprises a magnetoresistive-random-access-memory (MRAM) cell.

7. The multi-chip package of claim 1, wherein the semiconductor integrated-circuit (IC) chip further comprises a transistor configured to form a channel coupling to one of the plurality of non-volatile memory cells based on a voltage level at a gate terminal of the transistor.

8. The multi-chip package of claim 1, wherein the memory chip comprises a dynamic random-access memory (DRAM) chip.

9. The multi-chip package of claim 1 further comprising:

an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer, and a polymer layer between the first and second interconnection metal layers, wherein the first interconnection metal layer is connected to the second interconnection metal layer through multiple openings in the polymer layer;

a plurality of first copper bumps between the semiconductor integrated-circuit (IC) chip and the interconnection scheme, wherein each of the plurality of first copper bumps connects the semiconductor integrated-circuit (IC) chip to the first and second interconnection metal layers; and

a plurality of second copper bumps between the memory chip and the interconnection scheme, wherein each of the plurality of second copper bumps connects the memory chip to the first and second interconnection metal layers, wherein the memory chip couples to the semiconductor integrated-circuit (IC) chip through, in sequence, one of the plurality of second copper bumps, the second interconnection metal layer and one of the plurality of first copper bumps, wherein the semiconductor integrated-circuit (IC) chip is in a same plane as the memory chip.

10. The multi-chip package of claim 1, wherein each of the plurality of non-volatile memory cells comprises a first electrode, a resistive layer on the first electrode, and a second electrode on the resistive layer, wherein the resistive layer is between the first and second electrodes.

11. The multi-chip package of claim 10, wherein each of the plurality of non-volatile memory cells is configured to be programmed in one of a high resistance state and a low resistance state, wherein the low resistance state has a resistance lower than that of the high resistance state.

12. The multi-chip package of claim 10, wherein the resistive layer comprises hafnium oxide.

13. The multi-chip package of claim 10, wherein the resistive layer has a thickness between 1 and 20 nanometers.

14. The multi-chip package of claim 1, wherein each of the plurality of non-volatile memory cells comprises a first magnetic layer, an oxide layer on the first magnetic layer and a second magnetic layer on the oxide layer, wherein the oxide layer is between the first and second magnetic layers.

15. The multi-chip package of claim 14, wherein the oxide layer comprises magnesium oxide.

16. The multi-chip package of claim 14, wherein each of the plurality of non-volatile memory cells further comprises an antiferromagnetic layer under the first magnetic layer, wherein the first magnetic layer is between the antiferromagnetic layer and the oxide layer.

17. The multi-chip package of claim 1 further comprising a data bus coupling the semiconductor integrated-circuit (IC) chip to the memory chip, wherein the semiconductor integrated-circuit (IC) chip further comprises a plurality of I/O ports and at least one I/O-port selection pad configured to select a port from the plurality of I/O ports to output data from the semiconductor integrated-circuit (IC) chip to the data bus in a first clock cycle.

18. The multi-chip package of claim 17 further comprising a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip coupling to the data bus, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises an I/O port to receive the data, output by the port of the semiconductor integrated-circuit (IC) chip, from the data bus in the first clock cycle.

19. The multi-chip package of claim 17, wherein the at least one I/O-port selection pad is configured to select the port from the plurality of I/O ports to receive data from the data bus in a second clock cycle.

20. The multi-chip package of claim 19, wherein the data received by the port of the semiconductor integrated-circuit (IC) chip is output from the memory chip in the second clock cycle.

21. The multi-chip package of claim 1 further comprising a data bus coupling the semiconductor integrated-circuit (IC) chip to the memory chip, wherein the semiconductor integrated-circuit (IC) chip further comprises a plurality of I/O ports and at least one I/O-port selection pad configured to select a port from the plurality of I/O ports to receive data from the data bus to the semiconductor integrated-circuit (IC) chip.

22. The multi-chip package of claim 1 further comprising a data bus coupling the semiconductor integrated-circuit (IC) chip to the memory chip, wherein the semiconductor integrated-circuit (IC) chip further comprises an I/O port configured to receive data from the data bus to the semiconductor integrated-circuit (IC) chip, wherein the I/O port has a plurality of I/O circuits each having an input capacitance between 0.05 and 2 pF.

23. The multi-chip package of claim 1 further comprising a data bus coupling the semiconductor integrated-circuit (IC) chip to the memory chip, wherein the semiconductor integrated-circuit (IC) chip further comprises an I/O port configured to output data from the semiconductor integrated-circuit (IC) chip to the data bus, wherein the I/O port has a plurality of I/O circuits each having an output capacitance between 0.15 and 2 pF.

24. The multi-chip package of claim 1, wherein the data bit width is greater than or equal to 256.