Receiving circuit, semiconductor apparatus including the receiving circuit and semiconductor system using the receiving circuit

• US 10,523,216 B2
• Filed: 11/27/2018
• Issued: 12/31/2019
• Est. Priority Date: 04/17/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Hyun Bae
• Primary Examiner(s): Luu, An T
• Application Number:
  US16/201,315
• Publication Number:
  US 20190319629A1
• Time in Patent Office: 399 Days
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A semiconductor apparatus includes an internal clock generation circuit, a receiver, and a sampling circuit. The internal clock generation circuit generates a receiving clock signal and a sampling clock signal based on a reference clock signal, the sampling clock signal having a phase different from the receiving clock signal. The receiver receives an input signal in synchronization with the receiving clock signal and to generate an amplified signal. The sampling circuit samples the amplified signal in synchronization with the sampling clock signal to generate an output signal.

Claims

1. A receiving circuit comprising:

an internal clock generation circuit configured to generate a receiving clock signal and a sampling clock signal based on a reference clock signal, the sampling clock signal having a phase different from the receiving clock signal;

a receiver configured to receive an input signal in synchronization with the receiving clock signal and to generate an amplified signal; and

a sampling circuit configured to sample the amplified signal in synchronization with the sampling clock signal and to generate an output signal.

2. The receiving circuit according to claim 1, wherein the receiving clock signal has a pulse width corresponding to a valid window of the input signal.

3. The receiving circuit according to claim 1, wherein the sampling clock signal has the same pulse width as the reference clock signal.

4. The receiving circuit according to claim 1, wherein the internal clock generation circuit comprises:

a receiving clock generator configured to generate a delayed clock signal by delaying the reference clock signal by a predetermined time and a first time, and generate the receiving clock signal by delaying the delayed clock signal by a second time; and

a sampling clock generator configured to generate the sampling clock signal by delaying the delayed clock signal by the second time and a third time.

5. The receiving circuit according to claim 4, wherein a sum of the first time and the second time corresponds to a duration of the valid window of the input signal.

6. The receiving circuit according to claim 4, further comprising:

a clock buffer configured to receive an external clock signal; and

a divider configured to divide an output of the clock buffer and generate the reference clock signal.

7. The receiving circuit according to claim 1, further comprising:

a synchronization switch configured to output the amplified signal in synchronization with the receiving clock signal.

8. The receiving circuit according to claim 1, further comprising:

a precharge circuit configured to initialize a level of the amplified signal based on a precharge signal,

wherein the precharge signal has a phase later than the sampling clock signal.

9. A semiconductor apparatus comprising:

an internal clock generation circuit configured to generate a receiving clock signal which has a first pulse width and a sampling clock signal which has a second pulse width different from the first pulse width, the sampling clock signal having a phase later than the receiving clock signal, based on a reference clock signal;

a receiver configured to receive an input signal in synchronization with the receiving clock signal and to generate an amplified signal; and

a sampling circuit configured to sample the amplified signal in synchronization with the sampling clock signal and to generate an output signal.

10. The semiconductor apparatus according to claim 9, wherein the second pulse width is wider than the first pulse width.

11. The semiconductor apparatus according to claim 9, wherein the first pulse width corresponds to a duration of a valid window of the input signal.

12. The semiconductor apparatus according to claim 9, wherein the internal clock generation circuit comprises:

a receiving clock generator configured to generate a delayed clock signal by delaying the reference clock signal by a predetermined time and a first time, and generate the receiving clock signal by delaying the delayed clock signal by a second time; and

a sampling clock generator configured to generate the sampling clock signal by delaying the delayed clock signal by the second time and a third time.

13. The semiconductor apparatus according to claim 12, wherein a sum of the first time and the second time corresponds to the duration of the valid window of the input signal.

14. The semiconductor apparatus according to claim 12, further comprising:

a clock buffer configured to receive an external clock signal; and

a divider configured to divide an output of the clock buffer and generate the reference clock signal.

15. The semiconductor apparatus according to claim 12, further comprising:

a synchronization switch configured to output the amplified signal in synchronization with the receiving clock signal.

16. The semiconductor apparatus according to claim 12, further comprising:

a precharge circuit configured to initialize a level of the amplified signal based on a precharge signal, wherein the precharge signal has a phase later than the sampling clock signal.

17. A receiving circuit comprising:

a receiver configured to receive input data in synchronization with a receiving clock signal having a pulse width corresponding to a duration of a valid window of the input data and generate an amplified data;

a signal line configured to maintain a level of the amplified data based on the receiving clock signal; and

a sampling circuit configured to amplify a voltage level of the signal line in synchronization with a sampling clock signal and generate output data.

18. The receiving circuit according to claim 17, wherein the sampling clock signal has a pulse width wider than the receiving clock signal, and the sampling clock signal has a phase later than the receiving clock signal.

19. The receiving circuit according to claim 17, further comprising:

a synchronization switch configured to provide the amplified data to the signal line.

20. The receiving circuit according to claim 17, further comprising:

a capacitor configured to be coupled to the signal line and maintain a level of the amplified data.

21. The receiving circuit according to claim 17, further comprising:

a precharge circuit configured to initialize a voltage level of the signal line based on a precharge signal,

wherein the precharge signal has a phase later than the sampling clock signal.