Hybrid phase lock loop
First Claim
1. A phase lock loop (PLL), comprising:
- a first loop configured to provide a digital output signal based on a comparison of a reference input signal and an output signal of the PLL in a first operational mode of the PLL;
a second loop configured to provide an analog output signal based on a comparison of the reference input signal and a feedback signal that is proportional to the output signal of the PLL in a second operational mode of the PLL; and
an oscillator, coupled to the first loop and the second loop, configured to tune a frequency of the output signal of the PLL in accordance with the digital output signal in the first operational mode of the PLL and to tune an output phase of the output signal of the PLL in accordance with the analog output signal in the second operational mode of the PLL,wherein the first loop comprises an oscillator controller configured to disable the second loop in the first operational mode of the PLL.
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Accused Products
Abstract
Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.
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Citations
20 Claims
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1. A phase lock loop (PLL), comprising:
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a first loop configured to provide a digital output signal based on a comparison of a reference input signal and an output signal of the PLL in a first operational mode of the PLL; a second loop configured to provide an analog output signal based on a comparison of the reference input signal and a feedback signal that is proportional to the output signal of the PLL in a second operational mode of the PLL; and an oscillator, coupled to the first loop and the second loop, configured to tune a frequency of the output signal of the PLL in accordance with the digital output signal in the first operational mode of the PLL and to tune an output phase of the output signal of the PLL in accordance with the analog output signal in the second operational mode of the PLL, wherein the first loop comprises an oscillator controller configured to disable the second loop in the first operational mode of the PLL. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A phase lock loop (PLL), comprising:
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a first loop, implemented using digital components, configured to provide a digital output signal during a frequency tracking operation mode to tune a frequency of an output signal of the PLL; a second loop, implemented using analog components, configured to provide an analog output signal during a phase tracking operation mode to tune a phase of the output signal of the PLL; and an oscillator controller configured, in the frequency tracking operation mode, to; receive an error signal generated based on a comparison of a reference input signal and the output signal of the PLL; compare a trend of the error signal to a previous trend of the error signal, and enable the second loop upon detecting a change in the trend of the error signal to switch from the frequency tracking operation mode to the phase tracking operation mode. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for operating a phase lock loop (PLL), the method comprising:
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tuning a frequency of an output signal of the PLL using a digital tuning word generated by a digital controlled loop during a frequency tracking operation mode; receiving an error signal generated based on a comparison of a reference input signal and the output signal of the PLL; comparing a trend of the error signal to a previous trend of the error signal; and switching from the frequency tracking operation mode to a phase tracking operation mode to tune a phase of the output signal of the PLL using an analog output voltage generated by an analog controlled loop upon detecting a change in the trend of the error signal. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification