Hybrid phase lock loop

• US 10,523,221 B2
• Filed: 11/13/2018
• Issued: 12/31/2019
• Est. Priority Date: 11/30/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Tsung-Hsien, Chang, Chih-Hsien, Sheen, Ruey-Bin, Hsieh, Cheng-Hsiang
• Primary Examiner(s): Houston, Adam D
• Application Number:
  US16/189,482
• Publication Number:
  US 20190158102A1
• Time in Patent Office: 413 Days
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

Claims

1. A phase lock loop (PLL), comprising:

a first loop configured to provide a digital output signal based on a comparison of a reference input signal and an output signal of the PLL in a first operational mode of the PLL;

a second loop configured to provide an analog output signal based on a comparison of the reference input signal and a feedback signal that is proportional to the output signal of the PLL in a second operational mode of the PLL; and

an oscillator, coupled to the first loop and the second loop, configured to tune a frequency of the output signal of the PLL in accordance with the digital output signal in the first operational mode of the PLL and to tune an output phase of the output signal of the PLL in accordance with the analog output signal in the second operational mode of the PLL,

wherein the first loop comprises an oscillator controller configured to disable the second loop in the first operational mode of the PLL.

2. The PLL of claim 1, wherein the first loop further comprises:

a frequency detector configured to compare the reference input signal and the output signal of the PLL to provide a digital error signal, and

wherein the oscillator controller is further configured to provide a digital tuning word generated based upon the digital error signal to the oscillator to tune the frequency of the output signal of the PLL.

3. The PLL of claim 2, wherein the frequency detector and the oscillator controller are implemented using only digital components.

4. The PLL of claim 1, wherein the second loop comprises:

a feedback divider configured to scale the output signal of the PLL to provide the feedback signal; and

a phase frequency detector configured to detect a difference in phase between the reference input signal and the feedback signal.

5. The PLL of claim 4, wherein the feedback divider and the phase frequency detector are implemented using only analog components.

6. The PLL of claim 1, wherein the oscillator controller is configured to provide a tracking signal at a first logical level to disable the second loop in the first operational mode of the PLL and to switch the tracking signal to a second logical level to enable the second loop in the second operational mode of the PLL upon detecting a change in a trend of a difference between the reference input signal and the output signal of the PLL.

7. The PLL of claim 1, wherein the oscillator controller is further configured to:

set the analog output signal to a fixed voltage in the first operational mode of the PLL, and

adjust the analog output signal to track the reference input signal in the second operational mode of the PLL.

8. A phase lock loop (PLL), comprising:

a first loop, implemented using digital components, configured to provide a digital output signal during a frequency tracking operation mode to tune a frequency of an output signal of the PLL;

a second loop, implemented using analog components, configured to provide an analog output signal during a phase tracking operation mode to tune a phase of the output signal of the PLL; and

an oscillator controller configured, in the frequency tracking operation mode, to;

receive an error signal generated based on a comparison of a reference input signal and the output signal of the PLL;

compare a trend of the error signal to a previous trend of the error signal, and

enable the second loop upon detecting a change in the trend of the error signal to switch from the frequency tracking operation mode to the phase tracking operation mode.

9. The PLL of claim 8, wherein the first loop comprises:

a frequency detector configured to compare the reference input signal and the output signal of the PLL to provide a digital error signal, and

wherein the oscillator controller is further configured to provide a digital tuning word generated based upon the error signal to an oscillator to tune the frequency of the output signal of the PLL.

10. The PLL of claim 9, wherein the frequency detector and the oscillator controller are implemented using only the digital components.

11. The PLL of claim 8, wherein the second loop comprises:

a feedback divider configured to scale the output signal of the PLL to provide a feedback signal; and

a phase frequency detector configured to detect a difference in phase between the reference input signal and the feedback signal.

12. The PLL of claim 11, wherein the feedback divider and the phase frequency detector are implemented using only the analog components.

13. The PLL of claim 8, wherein the oscillator controller is configured to provide a tracking signal at a first logical level to disable the second loop in the frequency tracking operation mode and to switch the tracking signal to a second logical level to enable the second loop in the phase tracking operation mode upon detecting the change in the trend of the error signal.

14. The PLL of claim 8, wherein the oscillator controller is further configured to:

set the analog output signal to a fixed voltage in the frequency tracking operation mode, and

adjust the analog output signal to track the reference input signal in the phase tracking operation mode.

15. A method for operating a phase lock loop (PLL), the method comprising:

tuning a frequency of an output signal of the PLL using a digital tuning word generated by a digital controlled loop during a frequency tracking operation mode;

receiving an error signal generated based on a comparison of a reference input signal and the output signal of the PLL;

comparing a trend of the error signal to a previous trend of the error signal; and

switching from the frequency tracking operation mode to a phase tracking operation mode to tune a phase of the output signal of the PLL using an analog output voltage generated by an analog controlled loop upon detecting a change in the trend of the error signal.

16. The method of claim 15, further comprising:

comparing the reference input signal and the output signal of the PLL to provide a digital error signal, and

generating the digital tuning word based upon the digital error signal to the oscillator to tune the frequency of the output signal of the PLL.

17. The method of claim 15, further comprising:

scaling the output signal of the PLL to provide a feedback signal; and

detecting a difference in phase between the reference input signal and the feedback signal.

18. The method of claim 15, further comprising:

providing a tracking signal at a first logical level to disable the analog controlled loop in the frequency tracking operation mode, and

wherein the switching comprises;

switching the tracking signal to a second logical level to enable the analog controlled loop in the phase tracking operation mode upon detecting the change in the trend of the error signal.

19. The method of claim 15, further comprising:

setting the analog output signal to a fixed voltage in the frequency tracking operation mode, and

adjusting the analog output signal to track the reference input signal in the phase tracking operation mode.

20. The method of claim 15, further comprising:

disabling the analog controlled loop during the phase tracking operation mode.