Phase-locked loop circuit calibration method, memory storage device and connection interface circuit

• US 10,523,223 B2
• Filed: 05/08/2018
• Issued: 12/31/2019
• Est. Priority Date: 03/13/2018
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Yu, Chia-Hui, Chen, Wei-Yung
• Primary Examiner(s): Huson, Zachary K
• Application Number:
  US15/973,539
• Publication Number:
  US 20190288700A1
• Time in Patent Office: 602 Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/102 the additional signal being directly applied to the controlled loop oscillator

Abstract

A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and detecting the third signal to calibrate an electronic parameter of the phase-locked loop circuit.

Claims

1. A phase-locked loop circuit calibration method for a memory storage device comprising a rewritable non-volatile memory module, the phase-locked loop circuit calibration method comprising:

receiving a first signal from a host system;

generating a jitter signal by the memory storage device;

generating a second signal based on the first signal and the jitter signal;

performing a phase-lock operation on the second signal by a phase-locked loop circuit to generate a third signal; and

detecting the third signal to calibrate an electronic parameter of the phase-locked loop circuit,

wherein the first signal is an initial signal for establishing a connection between the host system and the memory storage device at a handshake stage.

2. The phase-locked loop circuit calibration method as claimed in claim 1, wherein a frequency of the jitter signal is not higher than a frequency of the first signal.

3. The phase-locked loop circuit calibration method as claimed in claim 1, wherein the step of detecting the third signal to calibrate the electronic parameter of the phase-locked loop circuit comprises:

adjusting at least one circuit parameter of the phase-locked loop circuit to calibrate a loop bandwidth or a loop jitter peaking of the phase-locked loop circuit.

4. The phase-locked loop circuit calibration method as claimed in claim 3, wherein the step of adjusting the at least one circuit parameter of the phase-locked loop circuit comprises:

adjusting at least one of a current, an impedance, and a gain on a closed-loop path of the phase-locked loop circuit.

5. The phase-locked loop circuit calibration method as claimed in claim 1, wherein the step of detecting the third signal to calibrate the electronic parameter of the phase-locked loop circuit comprises:

detecting signal quality evaluation information of the third signal; and

calibrating the electronic parameter of the phase-locked loop circuit based on the signal quality evaluation information.

6. The phase-locked loop circuit calibration method as claimed in claim 5, wherein the step of detecting the signal quality evaluation information of the third signal comprises:

obtaining a measured value of the third signal, wherein the measured value reflects one of an eye width of the third signal, an eye height of the third signal, and a jitter value of the third signal.

7. The phase-locked loop circuit calibration method as claimed in claim 1, wherein the step of detecting the third signal to calibrate the electronic parameter of the phase-locked loop circuit comprises:

setting a frequency of the jitter signal as a first frequency;

obtaining a first measured value of the third signal after performing the phase-lock operation on the second signal generated based on the first signal and the jitter signal having the first frequency;

determining a target value based on the first measured value;

setting the frequency of the jitter signal as a second frequency, wherein the second frequency differs from the first frequency;

obtaining a second measured value of the third signal after performing the phase-lock operation on the second signal generated based on the first signal and the jitter signal having the second frequency; and

calibrating the electronic parameter of the phase-locked loop circuit based on the target value and the second measured value.

8. The phase-locked loop circuit calibration method as claimed in claim 1, wherein the first signal further comprises a test signal for calibrating the phase-locked loop circuit at a test stage.

9. The phase-locked loop circuit calibration method as claimed in claim 1, wherein the jitter signal is adapted to adjust the first signal such that at least one rising edge or at least one falling edge of a bit stream of the second signal has a time shift of a different amount.

10. A memory storage device, comprising:

a connection interface unit, coupled to a host system;

a rewritable non-volatile memory module; and

a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,

wherein the connection interface unit comprises a phase-locked loop circuit,

wherein the connection interface unit is configured to receive a first signal from the host system,

wherein the connection interface unit is further configured to generate a jitter signal,

wherein the connection interface unit is further configured to generate a second signal based on the first signal and the jitter signal,

wherein the phase-locked loop circuit is configured to perform a phase-lock operation on the second signal to generate a third signal, and

wherein the connection interface unit is further configured to detect the third signal to calibrate an electronic parameter of the phase-locked loop circuit,

wherein the first signal is an initial signal for establishing a connection between the host system and the memory storage device at a handshake stage.

11. The memory storage device as claimed in claim 10, wherein a frequency of the jitter signal is not higher than a frequency of the first signal.

12. The memory storage device as claimed in claim 10, wherein the operation that the connection interface unit detects the third signal to calibrate the electronic parameter of the phase-locked loop circuit comprises:

adjusting at least one circuit parameter of the phase-locked loop circuit to calibrate a loop bandwidth or a loop jitter peaking of the phase-locked loop circuit.

13. The memory storage device as claimed in claim 12, wherein the operation that the connection interface unit adjusts the at least one circuit parameter of the phase-locked loop circuit comprises:

adjusting at least one of a current, an impedance, and a gain on a closed-loop path of the phase-locked loop circuit.

14. The memory storage device as claimed in claim 10, wherein the operation that the connection interface unit detects the third signal to calibrate the electronic parameter of the phase-locked loop circuit comprises:

detecting signal quality evaluation information of the third signal; and

calibrating the electronic parameter of the phase-locked loop circuit based on the signal quality evaluation information.

15. The memory storage device as claimed in claim 14, wherein the operation that the connection interface unit detects the signal quality evaluation information of the third signal comprises:

obtaining a measured value of the third signal, wherein the measured value reflects one of an eye width of the third signal, an eye height of the third signal, and a jitter value of the third signal.

16. The memory storage device as claimed in claim 10, wherein the operation that the connection interface unit detects the third signal to calibrate the electronic parameter of the phase-locked loop circuit comprises:

setting a frequency of the jitter signal as a first frequency;

obtaining a first measured value of the third signal after performing the phase-lock operation on the second signal generated based on the first signal and the jitter signal having the first frequency;

determining a target value based on the first measured value;

setting the frequency of the jitter signal as a second frequency, wherein the second frequency differs from the first frequency;

obtaining a second measured value of the third signal after performing the phase-lock operation on the second signal generated based on the first signal and the jitter signal having the second frequency; and

calibrating the electronic parameter of the phase-locked loop circuit based on the target value and the second measured value.

17. The memory storage device as claimed in claim 10, wherein the first signal further comprises a test signal for calibrating the phase-locked loop circuit at a test stage.

18. The memory storage device as claimed in claim 10, wherein the jitter signal is adapted to adjust the first signal such that at least one rising edge or at least one falling edge of a bit stream of the second signal has a time shift of a different amount.

19. A connection interface circuit for connecting a memory storage device to a host system, the connection interface circuit comprising:

a jitter control circuit, configured to generate a jitter signal;

a jitter generation circuit, coupled to the jitter control circuit and configured to receive a first signal from the host system and generate a second signal based on the first signal and the jitter signal;

a phase-locked loop circuit, coupled to the jitter generation circuit and configured to perform a phase-lock operation on the second signal to generate a third signal; and

a control circuit, coupled to the phase-locked loop circuit and the jitter control circuit and configured to detect the third signal to calibrate a circuit parameter of the phase-locked loop circuit,

wherein the first signal is an initial signal for establishing a connection between the host system and the memory storage device at a handshake stage.

20. The connection interface circuit as claimed in claim 19, wherein a frequency of the jitter signal is not higher than a frequency of the first signal.

21. The connection interface circuit as claimed in claim 19, wherein the operation that the control circuit detects the third signal to calibrate the electronic parameter of the phase-locked loop circuit comprises:

adjusting at least one circuit parameter of the phase-locked loop circuit to calibrate a loop bandwidth or a loop jitter peaking of the phase-locked loop circuit.

22. The connection interface circuit as claimed in claim 21, wherein the operation that the control circuit adjusts the at least one circuit parameter of the phase-locked loop circuit comprises:

adjusting at least one of a current, an impedance, and a gain on a closed-loop path of the phase-locked loop circuit.

23. The connection interface circuit as claimed in claim 19, wherein the operation that the control circuit detects the third signal to calibrate the electronic parameter of the phase-locked loop circuit comprises:

detecting signal quality evaluation information of the third signal; and

calibrating the electronic parameter of the phase-locked loop circuit based on the signal quality evaluation information.

24. The connection interface circuit as claimed in claim 23, wherein the operation that the control circuit detects the signal quality evaluation information of the third signal comprises:

obtaining a measured value of the third signal, wherein the measured value reflects one of an eye width of the third signal, an eye height of the third signal, and a jitter value of the third signal.

25. The connection interface circuit as claimed in claim 19, wherein the operation that the control circuit detects the third signal to calibrate the electronic parameter of the phase-locked loop circuit comprises:

setting a frequency of the jitter signal as a first frequency;

obtaining a first measured value of the third signal after performing the phase-lock operation on the second signal generated based on the first signal and the jitter signal having the first frequency;

determining a target value based on the first measured value;

setting the frequency of the jitter signal as a second frequency, wherein the second frequency differs from the first frequency;

obtaining a second measured value of the third signal after performing the phase-lock operation on the second signal generated based on the first signal and the jitter signal having the second frequency; and

calibrating the electronic parameter of the phase-locked loop circuit based on the target value and the second measured value.

26. The connection interface circuit as claimed in claim 19, wherein the first signal further comprises a test signal for calibrating the phase-locked loop circuit at a test stage.

27. The connection interface circuit as claimed in claim 19, wherein the jitter signal is adapted to adjust the first signal such that at least one rising edge or at least one falling edge of a bit stream of the second signal has a time shift of a different amount.