Second order harmonic cancellation for radio frequency front-end switches
First Claim
1. A radio frequency switch with a common pole and a plurality of throws, comprising:
- a first switch circuit connected to the common pole and a first signal line, the first switch circuit being selectively activatable in response to a first enable signal applied to the first switch circuit, and including a first harmonic suppressor and a first inductive element defining a first tank circuit blocking radio frequency signals at the common pole from reaching a first one of the plurality of throws with the first switch circuit in a deactivated state; and
a second switch circuit connected to the common pole and a second signal line, the second switch circuit being selectively activatable in response to a second enable signal applied to the second switch circuit, and including a second harmonic suppressor and a second inductive element defining a second tank circuit blocking radio frequency signals at the common pole from reaching a second one of the plurality of throws with the second switch circuit in a deactivated state.
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Accused Products
Abstract
A radio frequency switch circuit with improved harmonic suppression and low insertion loss has an antenna port and a plurality of signal ports. A plurality of transistor switch circuits, are connected to a respective one of the plurality of signal ports and to the antenna port. Each of the transistor switch circuits has a transistor, which in an off state, together with a harmonic suppression capacitor and a parallel inductor both connected thereto, define a tank circuit that suppresses RF signals applied to the corresponding transistor switch circuit from a different one of the transistor switch circuits. The harmonic suppression capacitor is tuned to distribute large signal voltage swings in the RF signal amongst parasitic diodes of the transistor.
9 Citations
20 Claims
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1. A radio frequency switch with a common pole and a plurality of throws, comprising:
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a first switch circuit connected to the common pole and a first signal line, the first switch circuit being selectively activatable in response to a first enable signal applied to the first switch circuit, and including a first harmonic suppressor and a first inductive element defining a first tank circuit blocking radio frequency signals at the common pole from reaching a first one of the plurality of throws with the first switch circuit in a deactivated state; and a second switch circuit connected to the common pole and a second signal line, the second switch circuit being selectively activatable in response to a second enable signal applied to the second switch circuit, and including a second harmonic suppressor and a second inductive element defining a second tank circuit blocking radio frequency signals at the common pole from reaching a second one of the plurality of throws with the second switch circuit in a deactivated state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A radio frequency switch with a common pole and a plurality of throws, comprising:
a plurality of switch circuits each corresponding to a respective of the plurality of throws, each of the switch circuits being connected to a signal line and an enable line and activatable in response to an enable signal applied to the enable line, each of the switch circuits further including a respective harmonic suppressor and inductor together defining respective tank circuits with the corresponding switch circuit being in a deactivated state that block radio frequency signals to the respective switch circuits. - View Dependent Claims (14, 15, 16, 17)
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18. A radio frequency switch element with a pole and throw, comprising:
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a switch transistor defined by a source, a drain, and a gate, and having an activated state and a deactivated state, the drain being connected to the pole and the source being connected to the throw; and a tank circuit connected across the switch transistor and blocking radio frequency signals on the drain with the switch transistor in the deactivated state. - View Dependent Claims (19, 20)
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Specification