Mechanisms for reducing latency and ghosting displays

• US 10,525,341 B2
• Filed: 04/24/2017
• Issued: 01/07/2020
• Est. Priority Date: 04/24/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hicks, Richmond, Ansari, Nausheen, Runyan, Arthur J., Biswal, Narayan
• Primary Examiner(s): Yodichkas, Aneeta
• Application Number:
  US15/494,765
• Publication Number:
  US 20180304151A1
• Time in Patent Office: 988 Days
• CPC Class Codes: A63F 13/25 Output arrangements for video game devices
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1446 display composed of modules, e.g. video walls
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

In one embodiment, an apparatus having an integrated circuit made of substrate, at least three light emitters arranged on the substrate, and driver circuitry located on the integrated circuit, the driver circuitry to drive an ultra low persistence display to remove ghosting and nausea.

Claims

1. A gaming system, comprising:

an image sensor to capture images;

an image signal processor (ISP) communicatively coupled to the image sensor to perform demosaicing;

a central processing unit (CPU) communicatively coupled to the ISP and to a graphics processing unit (GPU), wherein the combination of the CPU and the GPU operate to control a gaming application; and

a display coupled to the CPU, wherein the CPU to provide a first signal to the image sensor and a second signal to the display to synchronize the image sensor and the display to the gaming application being executed on the combination CPU and GPU to reduce latency.

2. The system of claim 1, wherein the first signal and the second signal are simultaneously sent to the image sensor and the display.

3. The system of claim 1, wherein the image sensor is synchronized to the same frame rate as the gaming application.

4. The system of claim 1, wherein the display is synchronized to an integer multiplier of the frequency of the gaming application.

5. The system of claim 4, wherein the refresh rate for the display is twice the frequency of the gaming application.

6. The system of claim 1, wherein the CPU varies a frame rate based on available compute and workload and uses the synchronization signals to maintain the image sensor and the display synchronization.

7. A method for reducing latency in a gaming system, comprising:

continuously sending, by the CPU (central processing unit) synchronization signals to an image sensor and a display, the synchronization signals based on the frequency of a game being executed on a combination CPU/GPU (graphics processing unit);

wherein the image sensor, upon receiving the synchronization signal from the CPU, captures a frame for processing by an image signal processor (ISP), and sends the frame to the CPU; and

wherein the display, upon receiving the synchronization signal from the CPU, refreshes the display with data from the CPU.

8. The method of claim 7, wherein the CPU sends two synchronization signals, one for the image sensor and one for the display.

9. The method of claim 7, wherein after a frame is sent to the CPU, the method further comprising waiting, by the image sensor, for the next synchronization signal.

10. The method of claim 7, wherein after the display is refreshed, the method further comprising waiting, by the display, for the next synchronization signal.

11. The method of claim 7, wherein the image sensor is synchronized to the same frame rate as the game.

12. The method of claim 7, wherein the display is synchronized to an integer multiplier of the game.

13. The method of claim 7, wherein separate synchronization signals are sent to the image sensor and the display.

14. The method of claim 13, wherein the separate synchronization signals are sent simultaneously.

15. At least one non-transitory computer readable medium, comprising a set of instructions, which when executed by at least one computing device cause the at least one computing device to:

continuously send synchronization signals to an image sensor and a display, the synchronization signals based on the frequency of a game being executed on a combination CPU/GPU (graphics processing unit);

wherein the image sensor, upon receiving the synchronization signal from the CPU, captures a frame for processing by an image signal processor (ISP), and sends the frame to the CPU; and

wherein the display, upon receiving the synchronization signal from the CPU, refreshes the display with data from the CPU.

16. The at least one non-transitory computer readable medium of claim 15, wherein to continuously send synchronization signals to an image sensor and a display further comprises instructions for the at least one computing device to send two synchronization signals, one for the image sensor and one for the display.

17. The at least one non-transitory computer readable medium of claim 15, wherein the image sensor is synchronized to the same frame rate as the game.

18. The at least one non-transitory computer readable medium of claim 15, wherein the display is synchronized to an integer multiplier of the frame rate of the game.

19. The at least one non-transitory computer readable medium of claim 15, wherein separate synchronization signals are sent simultaneously to the image sensor and the display.

20. The at least one non-transitory computer readable medium of claim 15, wherein the CPU varies a frame rate based on available compute and workload and uses the synchronization signals to maintain the image sensor and the display synchronization.

21. The at least one non-transitory computer readable medium of claim 15, wherein separate synchronization signals are sent to the image sensor and the display.

22. The at least one non-transitory computer readable medium of claim 15, further comprising instructions, which when executed by the at least one computing device cause the at least one computing device to instruct the image sensor to wait for the next synchronization signal.

23. The at least one non-transitory computer readable medium of claim 15, further comprising instructions, which when executed by the at least one computing device cause the at least one computing device to instruct the display, after the display has been refreshed, to wait for the next synchronization signal.