Vertical sense devices in vertical trench MOSFET

• US 10,527,654 B2
• Filed: 06/27/2017
• Issued: 01/07/2020
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: Vishay Siliconix LLC (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay Siliconix LLC (Vishay Intertechnology Incorporated)
• Inventors: Shibib, M. Ayman, Zhang, Wenjie
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US15/634,739
• Publication Number:
  US 20170299639A1
• Time in Patent Office: 924 Days
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G01R 19/15 Indicating the presence of current
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.

Claims

1. A semiconductor device comprising:

a main vertical trench metal oxide semiconductor field effect transistor (main-MOSFET) comprising;

a plurality of parallel main FET trenches, wherein said main FET trenches comprise a first electrode coupled to a gate of said main-MOSFET; and

a plurality of main mesas between said main FET trenches, wherein said main mesas comprise a main source and a main body of said main-MOSFET;

a current sense field effect transistor (sense-FET) comprising;

a plurality of sense-FET trenches, wherein each of said sense-FET trenches comprises a portion of one of said main FET trenches; and

a plurality of sense-FET mesas between said sense-FET trenches, wherein said sense-FET mesas comprise a sense-FET source that is electrically isolated from said main source of said main-MOSFET; and

an isolation trench configured to isolate said main-MOSFET from said sense-FET,

wherein said isolation trench is formed at an angle to, and intersects a plurality of said main FET trenches.

2. The semiconductor device of claim 1 wherein each of said plurality of parallel main FET trenches further comprises a main gate electrode coupled to said main gate of said main-MOSFET.

3. The semiconductor device of claim 2 wherein said main FET trenches comprise a first electrode coupled to said gate of said main-MOSFET and a second electrode electrically isolated from said main gate electrode.

4. The semiconductor device of claim 1 wherein portions of said main MOSFET surrounds said current sense FET on at least three sides.

5. The semiconductor device of claim 4 further comprising a surface isolation region free of surface metallization between said current sense-FET and said main MOSFET on said at least three sides.

6. The semiconductor device of claim 5 wherein portions of said surface isolation region are formed between isolation trenches crossing said parallel main trenches.

7. The semiconductor device of claim 1 further comprising:

at least two first isolation trenches crossing said parallel main trenches.

8. The semiconductor device of claim 7 further comprising:

a plurality of second isolation trenches, formed outside of an active area of said sense-FET, wherein each of said second isolation trenches comprises a portion of one of said main trenches.

9. A semiconductor device comprising:

a vertical trench main MOSFET (main-FET) configured to control a drain source current, wherein said main-FET comprises;

a plurality of parallel main FET trenches, wherein said main FET trenches comprise a first electrode coupled to a gate of said main-MOSFET; and

a plurality of main mesas between said main FET trenches, wherein said main mesas comprise a main source and a main body of said main-MOSFET;

a vertical trench current sensing FET (sense-FET) configured to produce a voltage corresponding to said drain source current, wherein said sense-FET comprises;

a plurality of sense-FET trenches, wherein each of said sense-FET trenches comprises a portion of one of said main FET trenches; and

a plurality of sense-FET mesas between said sense-FET trenches, wherein said sense-FET mesas comprise a sense-FET source that is electrically isolated from said main source of said main-MOSFET; and

an isolation trench configured to isolate said main-FET from said sense-FET,

wherein said isolation trench is formed at an angle to, and intersects a plurality of trenches of said main-FET.

10. The semiconductor device of claim 9 wherein vertical trenches of said main-FET comprise at least two vertically aligned electrodes, electrically insulated from one another.

11. The semiconductor device of claim 10 wherein a lower of said electrodes is coupled to a source of said main-FET.

12. The semiconductor device of claim 10 wherein an upper of said electrodes is coupled to a gate of said main-FET.

13. The semiconductor device of claim 9 wherein said angle is greater than 40 degrees.

14. The semiconductor device of claim 9 wherein said angle is substantially 90 degrees.

15. The semiconductor device of claim 9 wherein said sense-FET and said main-FET comprise common drain terminal but separate source and gate terminals.

16. A semiconductor device comprising:

a substrate;

a split gate vertical trench main MOSFET (main-FET), formed in said substrate, configured to control a drain source current,

wherein said main-FET comprises;

a main-FET source metal, disposed on the surface of said substrate, configured to couple a plurality of main-FET source regions to a main-FET source terminal;

a plurality of parallel main FET trenches, wherein said main FET trenches comprise a first electrode coupled to a gate of said main-MOSFET; and

a plurality of main mesas between said main FET trenches, wherein said main mesas comprise a main source and a main body of said main-MOSFET; and

a vertical trench current sensing FET (sense-FET), formed in said substrate, configured to produce a signal corresponding to said drain source current,

wherein said sense-FET is surrounded on at least three sides by said main-FET source metal.

17. The semiconductor device of claim 16 further comprising a sense-FET source metal, disposed on the surface of said substrate, configured to couple at least one sense-FET source region to at least one sense-FET source terminal.

18. The semiconductor device of claim 17 wherein said sense-FET source metal is electrically isolated from said main-FET source metal by a surface isolation region that is devoid of metal at the level of said main-FET source metal.

19. The semiconductor device of claim 18 comprising an insulator deposited on the surface of said substrate in said surface isolation region.

20. The semiconductor device of claim 19 wherein said insulator comprises borophosphosilicate glass.

21. The semiconductor device of claim 16 comprising at least two vertical trench current sensing FETs physically separated from one another.

22. The semiconductor device of claim 16 wherein said sense-FET and said main-FET comprise common gate and drain terminals.