Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating
First Claim
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1. A semiconductor memory array comprising:
- a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;
a bipolar device configured to store data when power is applied to said memory cell; and
a non-volatile memory comprising a bipolar resistive change element;
wherein said bipolar device is configured to be charged to a level indicative of a state of the memory cell based on resistivity of said bipolar resistive change element, upon restoration of power to said memory cell;
wherein said array is configured to perform a restore operation in parallel on said at least two of said memory cells.
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Abstract
A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
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Citations
20 Claims
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1. A semiconductor memory array comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include; a bipolar device configured to store data when power is applied to said memory cell; and a non-volatile memory comprising a bipolar resistive change element; wherein said bipolar device is configured to be charged to a level indicative of a state of the memory cell based on resistivity of said bipolar resistive change element, upon restoration of power to said memory cell; wherein said array is configured to perform a restore operation in parallel on said at least two of said memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include; a bipolar device configured to store data when power is applied to said memory cell; a non-volatile memory comprising a bipolar resistive change element; and a circuit configured to perform a restore operation on said at least two of said memory cells in parallel; wherein said bipolar device is configured to be charged to a level indicative of a state of the memory cell based on resistivity of said bipolar resistive change element, upon restoration of power to said memory cell. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
Specification