On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects

• US 10,529,439 B2
• Filed: 10/24/2017
• Issued: 01/07/2020
• Est. Priority Date: 10/24/2017
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Berger, Neal, Louie, Benjamin, El-Baraji, Mourad, Crudele, Lester
• Primary Examiner(s): Butler, Sarai E
• Application Number:
  US15/792,672
• Publication Number:
  US 20190122746A1
• Time in Patent Office: 805 Days
• Field of Search: 714 63, 714 624, 714 61
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/814 for optimized yield
• CPC Class Codes: G11C 29/816 for an application-specific layout

Abstract

A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.

Claims

1. A method for correcting bit defects in a memory, the method comprising:

executing a read before write operation in the memory, wherein the memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits, and wherein the read before write operation comprises;

reading a codeword; and

mapping defective bits in the codeword to redundant bits of the plurality of redundant bits based on a mapping scheme;

replacing the defective bits in the codeword with corresponding mapped redundant bits; and

executing a write operation with the corresponding redundant bits used in place of the defective bits.

2. The method of claim 1, wherein the reading the codeword and the mapping of the defective bits are performed substantially simultaneously.

3. The method of claim 1, further comprising:

verifying the write operation executed successfully by performing another read operation of the codeword following the write operation.

4. The method of claim 1, wherein the mapping comprises:

determining if a defective bit is an open circuit or a short circuit;

determining a position of the defective bit in the codeword; and

mapping a redundant bit of the plurality of redundant bits to the defective bit in accordance with the position of the defective bit.

5. The method of claim 1 further comprising:

executing a read operation following the write operation, wherein the read operation comprises mapping out the defective bits; and

replacing the defective bits in the codeword with corresponding redundant bits of the plurality of redundant bits using the mapping scheme that was used in the write operation.

6. The method of claim 5, wherein in accordance with the mapping scheme a defective bit is replaced with a corresponding redundant bit based on a relative position of the defective bit.

7. The method of claim 1, further comprising:

performing an ECC correction operation on results of the read operation to correct for transient defects not corrected using the plurality of redundant bits.

8. The method of claim 7, wherein the ECC correction operation is selected from a group consisting of:

BCH2, BCH3, Reed Solomon, Hamming and Low Density Parity Check (LDPC).

9. The method of claim 1 further comprising:

shorting ambiguous bits in the memory, wherein the ambiguous bits have ambiguous resistances between being high or low bits; and

wherein the mapping uses redundant bits to replace the ambiguous bits.

10. A method for correcting bit defects in a memory as described in claim 1, wherein the memory is STT-MRAM memory.

11. A method for correcting bit defects in a memory, the method comprising:

executing a read operation at an address in the memory, wherein the memory comprises a plurality of codewords, wherein each codeword comprises a respective plurality of redundant bits, and wherein the read operation comprises;

reading a codeword at the address; and

mapping defective bits in the codeword to redundant bits of the plurality of redundant bits in accordance with a mapping scheme; and

replacing the defective bits in the codeword with redundant bits of the plurality of redundant bits, wherein the defective bits are replaced with the redundant bits based on relative positions of the defective bits in accordance with the mapping scheme.

12. The method of claim 11, wherein the reading the codeword and the mapping of the defective bits are performed substantially simultaneously.

13. The method of claim 11, wherein the mapping comprises:

determining if a defective bit is an open circuit or a short circuit;

determining a position of the defective bit in the codeword; and

mapping a redundant bit to the defective bit based on the position.

14. The method of claim 11, further comprising:

performing an ECC correction operation on the results of the read operation to correct for transient defects not corrected using the plurality of redundant bits.

15. The method of claim 14, wherein the ECC correction operation is selected from a group consisting of:

BCH2, BCH3, Reed Solomon, Hamming and Low Density Parity Check (LDPC).

16. The method of claim 11 further comprising:

shorting ambiguous bits in the memory, wherein the ambiguous bits cannot be readily distinguished as high or low bits; and

wherein the mapping uses redundant bits to replace the ambiguous bits.

17. A method for correcting bit defects in a memory as described in claim 11, wherein the memory is STT-MRAM memory.

18. An apparatus for correcting bit defects in a memory, the apparatus comprising:

a processor;

a memory comprising a plurality of codewords, wherein each codeword comprises a respective plurality of redundant bits, and wherein the processor is configured to perform a write operation at an address, wherein the write operation comprises;

executing a read before write operation in the memory, wherein the read before write operation comprises;

reading a codeword at the address; and

mapping defective bits in the codeword to redundant bits of the plurality of redundant bits associated with the codeword;

replacing the defective bits in the codeword with corresponding redundant bits of the plurality of redundant bits; and

executing a write operation with the corresponding redundant bits used in place of the defective bits.

19. The apparatus of claim 18, wherein the reading the codeword and the mapping of the defective bits are performed simultaneously.

20. The apparatus of claim 18, wherein the write operation further comprises:

verifying the write operation executed successfully by performing another read operation at the address following the write operation.

21. The apparatus of claim 18, wherein in order to perform the mapping the processor is configured to:

determine if a defective bit is an open circuit or a short circuit;

determine a position of the defective bit in the codeword; and

map a redundant bit of the plurality of redundant bits to the defective bit in accordance with the position of the defective bit.

22. The apparatus of claim 18, wherein a defective bit is replaced with a corresponding redundant bit based on a relative position of the defective bit and the mapping scheme.

23. An apparatus for correcting bit defects in a memory as described in claim 18, wherein the memory is STT-MRAM memory.

24. A method of storing data into a memory, the method comprising:

writing a data word into an address of the memory, wherein the writing a data word comprises;

reading a codeword at the address to determine defective bits therein;

mapping the defective bits to corresponding redundant bits of a plurality of redundant bits associated with the codeword wherein the mapping is performed in accordance with a mapping scheme that is based on positions of the defective bits within the codeword; and

writing the data word into the codeword wherein the corresponding redundant bits are used to store bits of the data word instead of the defective bits of the codeword.

25. A method of storing data as described in claim 24 further comprising reading the data word from the codeword by:

detecting the defective bits of the codeword;

mapping the defective bits to the corresponding redundant bits of the plurality of redundant bits associated with the codeword in accordance with positions of the defective bits within the codeword and the mapping scheme; and

obtaining a result of the reading by reading the codeword and replacing the defective bits of the codeword with the corresponding redundant bits of the plurality of redundant bits associated with the codeword.

26. A method of storing data as described in claim 25 further comprising performing ECC correction on the result of the reading to correct for transient errors.

27. A method of storing data as described in claim 24 wherein the writing further comprises verifying the data word was written into the codeword and the corresponding defective bits associated with the codeword by performing a read-verify operation at the address.

28. A method of storing data as described in claim 24 wherein the memory is STT-MRAM memory and wherein further the mapping is performed on-the-fly as the memory is being used for mission mode functionality.

29. A method of storing data as described in claim 24 wherein the reading comprises:

reading the codeword;

detecting the defective bits in the codeword based on resistances associated with the defective bits as reported from sense amplifiers; and

using the mapping scheme to determine the corresponding redundant bits of the plurality redundant bits based on relative positions of the defective bits within the codeword.

30. A method of storing data as described in claim 24 further comprising performing the reading, the mapping and the writing each time a data word is written into the memory.

31. A method of storing data as described in claim 24 wherein one or more of the reading, the mapping and the writing are performed substantially simultaneously.

32. A method of storing data as described in claim 24 wherein one or more of the reading, the mapping and the writing are performed partially simultaneously.