Method and structure to construct cylindrical interconnects to reduce resistance

• US 10,529,662 B2
• Filed: 01/29/2018
• Issued: 01/07/2020
• Est. Priority Date: 01/29/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Briggs, Benjamin D., Rizzolo, Michael, Penny, Christopher J., Huang, Huai, Clevenger, Lawrence A., Shobha, Hosadurga
• Primary Examiner(s): Taylor, Earl N
• Application Number:
  US15/882,301
• Publication Number:
  US 20190237402A1
• Time in Patent Office: 708 Days
• CPC Class Codes: H01L 21/31056 the removal being a selective chemical etching step, e.g. selective dry etching through a mask
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76882 Reflowing or applying of pressure to better fill the contact hole
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry

Abstract

A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a bottom portion having a rounded surface, and an upper portion having linear surfaces;

depositing a liner layer on the rounded surface and on the linear surfaces of each of the plurality of trenches;

depositing a conductive layer on the liner layer in each of the plurality of trenches; and

removing upper portions of the conductive layer and the liner layer from the linear surfaces to form a rounded upper surface of the conductive layer corresponding to each of the plurality of trenches;

wherein the removing forms remaining portions of the conductive layer and the liner layer, the remaining portions form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

2. The method according to claim 1, wherein the liner layer is deposited using atomic layer deposition (ALD).

3. The method according to claim 1, further comprising:

recessing the dielectric layer to expose the rounded upper surface of the conductive layer corresponding to each of the plurality of trenches.

4. The method according to claim 3, wherein the removing and recessing is performed using an etch-back air-gap (EBAG) process.

5. The method according to claim 3, further comprising selectively depositing a plurality of metal cap layers on the exposed rounded upper surface of the conductive layer corresponding to each of the plurality of trenches.

6. The method according to claim 5, wherein the selective deposition of the plurality of metal cap layers is combined with a nitridation process to form a plurality of diffusion barriers.

7. The method according to claim 6, further comprising depositing an additional dielectric layer on the dielectric layer and on the conductive layer corresponding to each of the plurality of trenches and including the plurality of metal cap layers thereon.

8. The method according to claim 5, further comprising depositing dielectric cap layer on the dielectric layer and on the conductive layer corresponding to each of the plurality of trenches and including the plurality of metal cap layers thereon.

9. The method according to claim 1, further comprising selectively pre-filling a via extending from one of the plurality of trenches with a material of the conductive layer prior to depositing the conductive layer.

10. A method for manufacturing a semiconductor device, comprising:

forming a trench in a dielectric layer, wherein the trench comprises a bottom portion having a rounded surface, and an upper portion having linear surfaces; and

forming a conductive structure in the trench, wherein forming the conductive structure comprises;

depositing a liner layer on the rounded surface and on the linear surfaces of the trench;

depositing a conductive layer on the liner layer the trench; and

removing upper portions of the conductive layer and the liner layer from the linear surfaces to form a rounded upper surface of the conductive layer;

wherein the removing forms remaining portions of the conductive layer and the liner layer, the remaining portions form the conductive structure, and the conductive structure has a cylindrical shape.