Semiconductor structure and manufacturing method thereof

• US 10,529,666 B2
• Filed: 03/15/2017
• Issued: 01/07/2020
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Wu, Kai-Chiang, Lu, Chun-Lin
• Primary Examiner(s): Ahmad, Khaja
• Application Number:
  US15/459,691
• Publication Number:
  US 20180151501A1
• Time in Patent Office: 1,028 Days
• Field of Search: None
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias

Abstract

A semiconductor structure includes a first die; a first molding encapsulating the first die; a second die disposed over the first molding, and including a first surface, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface; and a second molding disposed over the first molding and surrounding the second die, wherein the first surface of the second die faces the first molding, and the second die is at least partially covered by the second molding.

Claims

1. A semiconductor structure, comprising:

a first die including a first surface and a second surface opposite to the first surface;

a first molding encapsulating the first die;

a second die disposed over the first molding, and including a third surface, a fourth surface opposite to the third surface, and a sidewall between the third surface and the fourth surface;

a third die disposed over the first molding, and including a fifth surface and a sixth surface opposite to the fifth surface, and a sidewall between the fifth surface and the sixth surface;

a fourth die disposed over the first molding, and including a seventh surface and a eight surface opposite to the seventh surface, and a plurality of sidewalls between the seventh surface and the eight surface;

a second molding disposed over the first molding and surrounding the second die, the third die and the fourth die; and

a dielectric layer disposed between the first molding and the second molding, wherein

the second surface of the first die faces the second die and is entirely in contact with the first molding, the third surface of the second die faces the first molding, the fourth surface of the second die is entirely exposed through the second molding, the sidewall of the second die is partially exposed through the second molding, the fifth surface of the third die faces the first molding, the sixth surface of the third die is partially exposed through the second molding and partially covered by the second molding, the plurality of sidewalls of the fourth die is entirely exposed through the second molding and a level of a top surface of the second molding is between a level of the sixth surface and a level of the eighth surface, wherein a bottom surface of the second molding, the third surface, the fifth surface and the seventh surface are coplanar, and

the second molding is in contact with the sidewall of the second die and the third die; and

the first molding and the second molding are separated from each other by the dielectric layer.

2. The semiconductor structure of claim 1, wherein the sidewall of the second die is partially covered by the second molding.

3. The semiconductor structure of claim 1, wherein the fourth surface of the second die is at a level higher than the level of the top surface of the second molding.

4. The semiconductor structure of claim 1, wherein the top surface of the second molding is at a level higher than the level of the sixth surface of the third die.

5. The semiconductor structure of claim 1, wherein the dielectric layer is disposed between the first molding and the second die, and an interconnect structure is disposed within the dielectric layer to electrically connect the second die with the first die.

6. The semiconductor structure of claim 1, further comprising a conductive via extending through the first molding.

13. The semiconductor structure of claim 1, wherein a thickness of the second molding is less than a thickness of the second die and greater than a thickness of the third die.

15. The semiconductor structure of claim 1, wherein a thickness of the second molding is consistent.

16. The semiconductor structure of claim 3, wherein the level of the top surface of the second molding is between the level of the fourth surface of the second die and the level of the sixth surface of the third die.

7. A semiconductor structure, comprising:

a first die including a first surface, a second surface opposite to the first surface, and a first sidewall between the first surface and the second surface;

a first molding encapsulating the first die;

a second die disposed over the first molding and including a third surface, a fourth surface opposite to the third surface, and a second sidewall between the third surface and the fourth surface;

a third die disposed over the first molding, and including a fifth surface and a sixth surface opposite to the fifth surface, and a third sidewall between the fifth surface and the sixth surface;

a fourth die disposed over the first molding, and including a seventh surface and a eight surface opposite to the seventh surface, and a fourth sidewall between the seventh surface and the eight surface;

a second molding disposed over the first molding and surrounding the second die, the third die and the fourth die; and

a dielectric layer disposed between the first molding and the second molding,

wherein the third surface faces the first molding, the second molding includes a recess having curved side surfaces, the second die is disposed within the recess, the fourth surface and the second sidewall of the second die are entirely exposed through the second molding, the fourth surface of the second die is at a level different from a level of a top surface of the second molding, the first sidewall of the first die is entirely in contact with the first molding, the fifth surface faces the first molding, the second molding covers a portion of the sixth surface and exposes a portion of the sixth surface, the level of the top surface of the second molding is between a level of the eight surface and a level of the sixth surface, wherein a bottom surface of the second molding, the third surface, the fifth surface and the seventh surface are coplanar,

wherein the second molding is in contact with the third sidewall and the fourth sidewall, and

the first molding and the second molding are separated from each other by the dielectric layer.

8. The semiconductor structure of claim 7, wherein the fourth surface of the second die is entirely exposed.

9. The semiconductor structure of claim 7, wherein a width of the recess is greater than a width of the second die.

10. The semiconductor structure of claim 7, wherein the recess is disposed over a portion of an interconnect structure.

14. The semiconductor structure of claim 7, wherein a thickness of the second molding is consistent.

17. The semiconductor structure of claim 7, wherein the level of the top surface of the second molding is between a level of the fourth surface of the second die and the level of the sixth surface of the third die.

11. A semiconductor structure, comprising:

a dielectric layer;

a first die;

a second die adjacent to the first die;

a third die adjacent to the first die; and

a molding, wherein the first die, the second die and the third die are molded in the molding with different mold coverage, a thickness of the molding is consistent,

thicknesses of the first die, the second die and the third die are different from each other,

the first die, the second die, the third die and the molding are disposed over a surface of the dielectric layer,

a portion of the surface of the dielectric layer is exposed through the molding,

a sidewall of the first die is partially covered by the molding and partially exposed through the molding,

a plurality of sidewalls of the second die is entirely exposed through the molding, and

a portion of a top surface of the third die is partially covered by the molding such that

a level of a top surface of the molding is between a level of a top surface of the first die and the top surface of the third die, wherein a bottom surfaces of the molding, the first die, the second die and third die are coplanar, and the molding is in contact with the sidewall of the first die and a sidewall of the third die.

12. The semiconductor structure of claim 11, wherein a sidewall of the third die is entirely covered by the molding.