Package structure and method for forming the same

• US 10,529,671 B2
• Filed: 07/03/2017
• Issued: 01/07/2020
• Est. Priority Date: 12/13/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Hsiao-Wen, Liu, Hsien-Wen, Jeng, Shin-Puu
• Primary Examiner(s): Muse, Ismail A
• Application Number:
  US15/640,695
• Publication Number:
  US 20180166396A1
• Time in Patent Office: 918 Days
• CPC Class Codes: H01L 21/0223 formation by oxidation, e.g. oxidation of the substrate
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/48 Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/118 Post-treatment of the bump connector
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/214 : Connecting portions
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3178 : Coating or filling in grooves made in the semiconductor body
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

Package structures and methods for forming the same are provided. A fan-out package structure includes a semiconductor substrate. The package structure also includes a connector over a top surface of the semiconductor substrate. The package structure further includes a buffer layer surrounding the connector and overlying a sidewall of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the buffer layer. The buffer layer is between the encapsulation layer and the sidewall of the semiconductor substrate. The package structure also includes a redistribution layer (RDL) over the buffer layer and the encapsulation layer. The redistribution layer is electrically connected to the connector.

Claims

1. A method for forming a package structure, comprising:

providing a semiconductor substrate comprising a first surface and a second surface opposite to the first surface;

partially removing the semiconductor substrate from the first surface to form a trench;

forming a first buffer layer over the semiconductor substrate to fill the trench;

attaching the first buffer layer and the second surface of the semiconductor substrate to an adhesive layer;

cutting the first buffer layer and the adhesive layer to form a die comprising the semiconductor substrate, the first buffer layer and the adhesive layer, wherein the first buffer layer covers a sidewall of the semiconductor substrate; and

forming an encapsulation layer surrounding the die, wherein the first buffer layer separates the semiconductor substrate from the encapsulation layer, wherein a top surface of the adhesive layer is in direct contact with the second surface of the semiconductor substrate and the first buffer layer, and a bottom surface of the adhesive layer is level with a bottom surface of the encapsulation layer.

2. The method for forming a package structure as claimed in claim 1, further comprising:

thinning the semiconductor substrate from the second surface until the first buffer layer filled in the trench is exposed before the cutting of the first buffer layer.

3. The method for forming a package structure as claimed in claim 1, further comprising:

thinning the semiconductor substrate from the second surface until the trench is exposed, wherein the first buffer layer is formed after the thinning of the semiconductor substrate.

4. The method for forming a package structure as claimed in claim 1, wherein the semiconductor substrate further comprises a third surface exposed through the trench, and the method further comprises:

oxidizing the third surface exposed through the trench before the formation of the first buffer layer.

5. The method for forming a package structure as claimed in claim 1, further comprising:

depositing a second buffer layer over the first surface of the semiconductor substrate before the formation of the first buffer layer, wherein the second buffer layer extends into the trench.

6. The method for forming a package structure as claimed in claim 1, further comprising:

thinning the semiconductor substrate from the second surface until the trench is exposed; and

depositing a second buffer layer extending from the second surface of the semiconductor substrate into the trench before the formation of the first buffer layer.

7. The method for forming a package structure as claimed in claim 1, further comprising:

forming a connector over the first surface of the semiconductor substrate;

forming a second buffer layer over the first surface of the semiconductor substrate to surround the connector;

partially removing the second buffer layer so that the trench penetrates through the second buffer layer into the semiconductor substrate; and

thinning the second buffer layer until the connector is exposed after the formation of the first buffer layer.

8. The method for forming a package structure as claimed in claim 1, further comprising:

forming a connector over the first surface of the semiconductor substrate, wherein a top surface of the connector is level with a top surface of the first buffer layer.

9. A method for forming a package structure, comprising:

forming a semiconductor substrate having a trench on a top surface of the semiconductor substrate;

forming a first buffer layer over the semiconductor substrate to fill the trench;

attaching an adhesive layer to a bottom surface of the semiconductor substrate;

cutting the first buffer layer and the adhesive layer along the trench, wherein a portion of the adhesive layer extends outwardly from a sidewall of the semiconductor substrate so that a top surface of the adhesive layer is in direct contact with the semiconductor substrate and the first buffer layer;

forming an encapsulation layer surrounding the first buffer layer and the adhesive layer, wherein the encapsulation layer is in direct contact with a sidewall of the adhesive layer; and

forming a redistribution layer over the first buffer layer and the encapsulation layer.

10. The method for forming a package structure as claimed in claim 9, wherein the first buffer layer and the encapsulation layer comprise different materials.

11. The method for forming a package structure as claimed in claim 9, wherein the first buffer layer is between the encapsulation layer and the sidewall of the semiconductor substrate.

12. The method for forming a package structure as claimed in claim 9, wherein the first buffer layer overlies the portion of the adhesive layer extending outwardly from the sidewall of the semiconductor substrate.

13. The method for forming a package structure as claimed in claim 9, wherein an interface between the adhesive layer and the encapsulation layer is substantially coplanar with an interface between the first buffer layer and the encapsulation layer.

14. The method for forming a package structure as claimed in claim 9, further comprising:

forming a second buffer layer covering the sidewall of the semiconductor substrate, wherein the first buffer layer surrounds the second buffer layer.

15. The method for forming a package structure as claimed in claim 14, wherein the second buffer layer extends from the sidewall of the semiconductor substrate to a bottom surface of the semiconductor substrate.

16. The method for forming a package structure as claimed in claim 9, further comprising:

forming a connector over the semiconductor substrate, wherein the redistribution layer is electrically connected to the connector; and

forming a second buffer layer over the top surface of the semiconductor substrate, wherein the connector is embedded in the second buffer layer and separated from the first buffer layer by the second buffer layer.

20. The method for forming a package structure as claimed in claim 9, wherein a bottom surface of the adhesive layer is substantially coplanar with a bottom surface of the encapsulation layer.

17. A method for forming a package structure, comprising:

forming a semiconductor substrate having a trench on a top surface of the semiconductor substrate;

forming a first buffer layer over the semiconductor substrate, wherein the first buffer layer covers the top surface and a sidewall of the semiconductor substrate;

depositing a second buffer layer extending from a bottom surface of the semiconductor substrate into the trench before the formation of the first buffer layer;

forming an encapsulation layer surrounding the first buffer layer, wherein the encapsulation layer and the sidewall of the semiconductor substrate are separated by the first buffer layer;

forming a passivation layer over the encapsulation layer; and

forming a redistribution layer over the passivation layer, wherein the redistribution layer is electrically connected to the semiconductor substrate.

18. The method for forming a package structure as claimed in claim 17, wherein forming the first buffer layer comprises:

forming the first buffer layer to fill the trench; and

cutting the first buffer layer.

19. The method for forming a package structure as claimed in claim 18, further comprising:

thinning a bottom surface of the semiconductor substrate until the first buffer layer filled in the trench is exposed before the cutting of the first buffer layer.