Semiconductor device

• US 10,529,678 B2
• Filed: 03/26/2015
• Issued: 01/07/2020
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Deutschland GmbH (Intel Corporation)
• Inventors: Kutter, Christoph, Soutschek, Ewald, Meyer-Berg, Georg
• Primary Examiner(s): Hoang, Tuan A
• Application Number:
  US14/669,219
• Publication Number:
  US 20150200174A1
• Time in Patent Office: 1,748 Days
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/12 Mountings, e.g. non-detachable insulating substrates
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Claims

1. A device, comprising:

a semiconductor chip having a first conduction element;

a printed circuit board having second and third conduction elements, the printed circuit board having a top side and a bottom side, wherein the second conduction element extends through the printed circuit board from the top side of the printed circuit board to the bottom side of the printed circuit board, and wherein the third conduction element extends across the top side of the printed circuit board;

external connection elements connected directly to the first, second and third conduction elements,

wherein the external connection elements are configured to form an electrical path between the first, second and third conduction elements, wherein the external connection elements comprise first, second and third solder balls aligned along a same linear direction, and the electrical path is formed from the second conduction element to the first solder ball, to the first conduction element, to the second solder ball, to the third conduction element, to the third solder ball, and wherein centers of the first, second and third solder balls are co-planar with one another; and

a fourth solder ball coupled to the second conduction element at the bottom side of the printed circuit board.

2. The device of claim 1, wherein the printed circuit board further comprises a fourth conduction element located between and electrically isolated from the second and third conduction elements, and a vertical projection of the fourth conduction element crosses the first conduction element.

3. The device of claim 2, wherein the second, third, and fourth conduction elements are formed from a common conduction layer.

4. The device of claim 1, wherein the external connection elements are located at positions defining an array.