Accommodating imperfectly aligned memory holes
First Claim
1. A method of forming a memory cell, the method comprising:
- forming a silicon nitride spacer on a ledge of a patterned substrate positioned in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating oxide and nitride layers defining a vertical memory hole there through, wherein sidewalls of the vertical memory hole include a conformal coating and a first polysilicon layer overlying the conformal coating, and wherein the vertical stack comprises a bottom portion and a top portion laterally misaligned to form the ledge;
removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer;
removing a bottom portion of the conformal coating using a gas-phase etch;
removing the silicon nitride spacer from the ledge using a gas-phase etch; and
forming a second polysilicon layer on the first polysilicon layer.
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Accused Products
Abstract
Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.
2035 Citations
19 Claims
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1. A method of forming a memory cell, the method comprising:
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forming a silicon nitride spacer on a ledge of a patterned substrate positioned in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating oxide and nitride layers defining a vertical memory hole there through, wherein sidewalls of the vertical memory hole include a conformal coating and a first polysilicon layer overlying the conformal coating, and wherein the vertical stack comprises a bottom portion and a top portion laterally misaligned to form the ledge; removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer; removing a bottom portion of the conformal coating using a gas-phase etch; removing the silicon nitride spacer from the ledge using a gas-phase etch; and forming a second polysilicon layer on the first polysilicon layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a memory cell, the method comprising:
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forming sacrificial silicon oxide in a bottom portion of a vertical memory hole through a patterned substrate in a substrate processing chamber, wherein the patterned substrate comprises a vertical stack of alternating oxide and nitride layers defining the vertical memory hole, wherein sidewalls of the vertical memory hole include an inner layer coating, wherein the patterned substrate further comprises a first polysilicon layer formed on the inner layer coating;
wherein the vertical stack comprises the bottom portion and a top portion laterally misaligned to form a ledge;forming conformal silicon nitride on exposed portions of the first polysilicon layer exposed by the sacrificial silicon oxide; removing the sacrificial silicon oxide; removing a bottom portion of the first polysilicon layer by reactive ion etching the bottom portion of the first polysilicon layer while retaining sidewall portions of the first polysilicon layer; removing a bottom portion of the inner layer coating using a gas-phase etch; removing the conformal silicon nitride; and forming a second polysilicon layer on the first polysilicon layer producing electrical contact between the second polysilicon layer and underlying silicon. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method of forming a memory cell, the method comprising:
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forming a bottom portion of a compound stack of alternating silicon oxide and silicon nitride slabs; forming a bottom portion of a memory hole through the bottom portion of the compound stack by patterning the bottom portion of the compound stack; filling the bottom portion of the compound stack with doped silicon oxide; forming a top portion of the compound stack of alternating silicon oxide and silicon nitride slabs; forming a top portion of a memory hole through the top portion of the compound stack by patterning the top portion of the compound stack and exposing the doped silicon oxide; and selectively removing the doped silicon oxide with a gas-phase etch which retains material in the alternating silicon oxide and silicon nitride slabs in each of the top portion and the bottom portion, wherein the bottom portion and the top portion of the compound stack are fluidly coupled and the top portion is laterally displaced from the bottom portion. - View Dependent Claims (16, 17, 18, 19)
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Specification