Semiconductor device

• US 10,529,814 B2
• Filed: 05/10/2018
• Issued: 01/07/2020
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Naito, Tatsuya
• Primary Examiner(s): Ho, Hoang-Quan T
• Assistant Examiner(s): Stowe, Scott
• Application Number:
  US15/976,829
• Publication Number:
  US 20180269294A1
• Time in Patent Office: 607 Days
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode.

Claims

1. A vertical transistor comprising:

an active region of the vertical transistor formed in a semiconductor substrate of a first conductivity type, the active region comprising;

a base region of a second conductivity type,

a first vertical gate trench adjacent to the base region, and

a first gate electrode embedded entirely in the first vertical gate trench;

an edge termination region surrounding the active region, the edge termination region comprising;

a second vertical gate trench surrounding the active region around an outer periphery portion of the active region;

a second gate electrode embedded entirely in the second vertical gate trench;

a gate wiring layer formed overlying at least a portion of the active region and at least a portion of the edge termination region, the gate wiring layer electrically connecting the first gate electrode to the second gate electrode; and

a well region of the second conductivity type, the well region including at least a bottom portion of the second vertical gate trench and extending below the first vertical gate trench, the well region being deeper than the base region and having a dopant concentration that is higher than a dopant concentration of the base region.

2. The vertical transistor according to claim 1, wherein:

the first vertical gate trench is provided with a “

U”

shape whose long direction is orthogonal to a long direction of the gate wiring layer, and a short direction of the “

U”

shape extends in the long direction below the gate wiring layer; and

the gate wiring layer is directly connected to the first gate electrode in the first vertical gate trench in the short direction.

3. The vertical transistor according to claim 1, wherein:

the first vertical gate trench extends in a first direction below an extending portion of the gate wiring layer,

the gate wiring layer is directly connected to the first gate electrode of the first vertical gate trench extending in the first direction, and

the first vertical gate trench is provided with a lattice shape formed by intersections of portions extending in the first direction and portions extending orthogonal to the first direction.

4. The vertical transistor according to claim 1, further comprising:

a collector region of the second conductivity type below and vertically separated from the well region at least by a buffer region; and

a collector electrode formed on a bottom surface of the collector region.

5. The vertical transistor according to claim 1, wherein

the gate wiring layer is an emitter electrode provided on top of the first gate electrode, and

the emitter electrode is divided into a plurality of pieces.

6. The vertical transistor according to claim 5, further comprising:

a protective film on top of the emitter electrode; and

a metal layer that is electrically separated from the emitter electrode by the protective film and is electrically connected to a plurality of other emitter electrodes on top of a respective plurality of other emitter electrodes associated with other vertical transistors.

7. The vertical transistor according to claim 1, further comprising:

a dummy trench separated from the first vertical gate trench by the base region.

8. The vertical transistor according to claim 7, further comprising:

an interlayer insulating film that is provided under the gate wiring layer, wherein

in a region outside of the first vertical gate trench and the dummy trench, the interlayer insulating film directly contacts the gate wiring layer on a first surface and directly contacts the well region on a second surface opposite the first surface.

9. The vertical transistor according to claim 7, further comprising:

an interlayer insulating film in direct contact with the well region, wherein

the gate wiring layer is an emitter electrode that is provided in contact with an upper surface of the interlayer insulating film,

the emitter electrode covers a plurality of other first vertical gate trenches associated with other vertical transistors, and

in a region outside of the first vertical gate trench and the dummy trench, the interlayer insulating film directly contacts the emitter electrode.

10. The vertical transistor according to claim 9, wherein:

the well region is directly beneath the emitter electrode in an extending portion, the well region being deeper than the first vertical gate trench and the dummy trench.

11. A vertical transistor comprising:

an active region of the vertical transistor formed in a semiconductor substrate of a first conductivity type, the active region comprising;

a base region of a second conductivity type,

a first vertical gate trench adjacent to the base region, and

a first gate electrode embedded entirely in the first vertical gate trench;

an edge termination region surrounding the active region, the edge termination region comprising;

a second vertical gate trench surrounding the active region around an outer periphery portion of the active region;

a second gate electrode embedded entirely in the second vertical gate trench;

a gate wiring layer formed overlying at least a portion of the active region and at least a portion of the edge termination region, the gate wiring layer electrically connecting the first gate electrode to the second gate electrode; and

a dummy trench separated from the first vertical gate trench by the base region,

wherein the dummy trench crosses below and orthogonally to a long direction of the gate wiring layer.

12. A vertical transistor comprising:

an active region of the vertical transistor formed in a semiconductor substrate of a first conductivity type, the active region comprising;

a base region of a second conductivity type,

a first vertical gate trench adjacent to the base region, and

a first gate electrode embedded entirely in the first vertical gate trench; and

an edge termination region surrounding the active region, the edge termination region comprising;

a second vertical gate trench surrounding the active region around an outer periphery portion of the active region;

a second gate electrode embedded entirely in the second vertical gate trench; and

a gate wiring layer formed overlying at least a portion of the active region and at least a portion of the edge termination region, the gate wiring layer electrically connecting the first gate electrode to the second gate electrode,

wherein an extending portion of the gate wiring layer is provided extending from one side of the outer periphery portion of the active region to another side of the outer periphery portion of the active region opposite the one side.