Gate structure having designed profile

• US 10,529,822 B2
• Filed: 07/14/2017
• Issued: 01/07/2020
• Est. Priority Date: 10/01/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Kai-Li, Chang, Che-Cheng
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US15/650,387
• Publication Number:
  US 20170317185A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Semiconductor structures are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. In addition, a sidewall of the gate structure has a top portion having a first inclination, a middle portion having a second inclination, and a bottom portion having a third inclination, and the first inclination, the second inclination, and the third inclination are different from one another.

Claims

1. A semiconductor structure, comprising:

a substrate; and

a gate structure formed over the substrate, wherein the gate structure comprises a gate electrode layer and a gate dielectric layer, and the gate dielectric layer is formed on both sides of the gate electrode layer;

wherein a sidewall of the gate dielectric layer has a top portion having a first inclination, a middle portion having a second inclination, and a bottom portion having a third inclination, and the first inclination, the second inclination, and the third inclination are different from one another, and the gate dielectric layer has a flat bottom surface, and

wherein a bottom surface of the gate electrode layer is greater than a top surface of the gate electrode layer.

2. The semiconductor structure as claimed in claim 1, wherein the gate structure has a first width, a second width, and a third width, and wherein the first width is a width measured from an intersection of a top portion and a middle portion of a sidewall of the gate structure, the second width is a width measured from an intersection of the middle portion and a bottom portion of the sidewall of the gate structure, a third width is a width measured from a bottom surface of the gate structure, and the second width is larger than the first width.

3. The semiconductor structure as claimed in claim 2, wherein the second width is larger than the third width.

4. The semiconductor structure as claimed in claim 2, wherein a ratio of the second width to the first width is in a range from about 1.01 to about 1.51.

5. The semiconductor structure as claimed in claim 2, wherein a ratio of the second width to the third width is in a range from about 1.01 to about 1.44.

6. The semiconductor structure as claimed in claim 1, wherein an angle between the middle portion and the bottom portion of the sidewall of the gate dielectric layer measured from an inner side of the gate structure is smaller than 180°

.

8. The semiconductor structure as claimed in claim 1, wherein a top surface of the gate dielectric layer is leveled with the top surface of the gate electrode layer, and a top surface of the substrate is leveled with a bottom surface of the gate dielectric layer.

7. A semiconductor structure, comprising:

a substrate;

a metal gate structure formed over the substrate; and

spacers formed on sidewalls of the metal gate structure,

wherein the metal gate structure has a top portion, a middle portion, and a bottom portion, the middle portion is wider than both the top portion and the bottom portion, and wherein the metal gate structure comprises a gate electrode layer, a work function layer and a gate dielectric layer, the work function layer is formed on both sides of the gate electrode layer, and the gate dielectric layer is formed on both sides of the work function layer, and a top surface of the work function layer is leveled with a top surface of the gate dielectric layer.

9. The semiconductor structure as claimed in claim 7, wherein an angle between a bottom surface of the metal gate structure and a sidewall of the bottom portion of the metal gate structure is larger than 90°

.

10. The semiconductor structure as claimed in claim 7, wherein an angle between a sidewall of the middle portion and a sidewall of the bottom portion of the metal gate structure is in a range from about 120°

to about 170°

.

11. The semiconductor structure as claimed in claim 7, wherein a ratio of a width of the middle portion to a width of the bottom portion is in a range from about 1.01 to about 1.44.

12. The semiconductor structure as claimed in claim 7, wherein the spacers are in direct contact with the gate dielectric layer, wherein an angle between a bottom surface of the spacers and a bottom portion of a sidewall of the gate dielectric layer is smaller than 90°

.

13. A semiconductor structure, comprising:

a substrate; and

a gate structure having curved sidewalls formed over the substrate;

wherein each curved sidewall has a top portion, a middle portion, and a bottom portion, and an angle between the middle portion and the bottom portion of the curved sidewall measured from an inner side of the gate structure is smaller than 180°

, and

wherein the top portion of the curved sidewall has a first inclination measured from the inner side of the gate structure, the middle portion of the curved sidewall has a second inclination measured from the inner side of the gate structure, and the first inclination is greater than the second inclination.

14. The semiconductor structure as claimed in claim 13, wherein a bottom portion of the curved sidewall has a third inclination measured from the inner side of the gate structure, and the third inclination is greater than the first inclination.

15. The semiconductor structure as claimed in claim 13, wherein the gate structure has a first width at a top surface of the gate structure, a second width at a middle portion of the gate structure, and a third width at a bottom surface of the gate structure, and the second width is greater than both the first width and the third width.

16. The semiconductor structure as claimed in claim 15, wherein a ratio of the second width to the first width is in a range from about 1.01 to about 1.51.

17. The semiconductor structure as claimed in claim 15, wherein a ratio of the second width to the third width is in a range from about 1.01 to about 1.44.

18. The semiconductor structure as claimed in claim 15, wherein the third width is greater than the first width.

19. The semiconductor structure as claimed in claim 13, wherein the gate structure comprises a gate dielectric layer, a work function metal layer, and a gate electrode layer.

20. The semiconductor structure as claimed in claim 13, wherein an angle between a bottom surface of the gate structure and a bottom portion of the curved sidewall is in a range from about 91°

to about 91.8°

.