Methods, apparatus, and system for forming epitaxial formations with reduced risk of merging

• US 10,529,831 B1
• Filed: 08/03/2018
• Issued: 01/07/2020
• Est. Priority Date: 08/03/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Gao, Qun, Stoker, Matthew W., Huang, Haigou
• Primary Examiner(s): Le, Thao P
• Application Number:
  US16/054,881
• Time in Patent Office: 522 Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

At least one method, apparatus and system providing semiconductor devices comprising a semiconductor substrate; a first fin and a second fin on the semiconductor substrate; a first epitaxial formation on the first fin and having an inner surface oriented toward the second fin and an outer surface oriented away from the second fin; a second epitaxial formation on the second fin and having an inner surface oriented toward the first fin and an outer surface oriented away from the first fin; and a conformal dielectric layer on at least portions of the inner and outer surfaces of the first epitaxial formation, on at least portions of the inner and outer surfaces of the first epitaxial formation and the second epitaxial formation, and merged between the inner surface of the first epitaxial formation and inner surface of the second epitaxial formation.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a first fin and a second fin on the semiconductor substrate;

a first epitaxial formation on the first fin and having an inner surface oriented toward the second fin and an outer surface oriented away from the second fin;

a second epitaxial formation on the second fin and having an inner surface oriented toward the first fin and an outer surface oriented away from the first fin; and

a conformal dielectric layer on at least portions of the inner and outer surfaces of the first epitaxial formation, on at least portions of the inner and outer surfaces of the first epitaxial formation and the second epitaxial formation, and merged between the inner surface of the first epitaxial formation and inner surface of the second epitaxial formation, wherein a top of the merged conformal dielectric layer between the inner surfaces of the first and second epitaxial formations is higher than a top of the conformal dielectric layer on the outer surfaces of the first and second epitaxial formations.

2. The semiconductor device of claim 1, further comprising an insulating region around and between the first fin and the second fin, wherein an upper portion of the first fin and an upper portion of the second fin are above the insulating region.

3. The semiconductor device of claim 2, wherein the conformal dielectric layer is further on at least a portion of a surface of the insulating region, on an inner surface of the upper region of the first fin oriented toward the second fin, on an outer surface of the upper region of the first fin oriented away from the second fin, on an inner surface of the upper region of the second fin oriented toward the first fin, and on an outer surface of the upper region of the second fin oriented away from the first fin.

4. The semiconductor device of claim 1, further comprising:

a third epitaxial formation on the first epitaxial formation; and

a fourth epitaxial formation on the second epitaxial formation;

wherein the third and fourth epitaxial formations are not disposed on the conformal dielectric layer.

5. The semiconductor device of claim 1, wherein the conformal dielectric layer comprises a material selected from nitrides and oxides.

6. The semiconductor device of claim 1, wherein the first fin and the second fin are less than 25 nm apart.

7. A system, comprising:

a semiconductor device processing system to manufacture a semiconductor device; and

a processing controller operatively coupled to the semiconductor device processing system, the processing controller configured to control an operation of the semiconductor device processing system;

wherein the semiconductor device processing system is adapted to;

form a first fin and a second fin on the semiconductor substrate;

form, on the first fin, a first epitaxial formation having an inner surface oriented toward the second fin and an outer surface oriented away from the second fin;

form, on the second fin, a second epitaxial formation and having an inner surface oriented toward the first fin and an outer surface oriented away from the first fin;

deposit a conformal dielectric material at least on the first epitaxial formation, the second epitaxial formation, an inner surface of the upper region of the first fin oriented toward the second fin, an outer surface of the upper region of the first fin oriented away from the second fin, an inner surface of the upper region of the second fin oriented toward the first fin, and an outer surface of the upper region of the second fin oriented away from the first fin, wherein the conformal dielectric material merges between the inner surface of the first epitaxial formation and inner surface of the second epitaxial formation and pinches off a space between the first fin and the second fin; and

etch the conformal dielectric material to form a conformal dielectric layer on at least portions of the inner and outer surfaces of the first epitaxial formation and the second epitaxial formation, and merged between the inner surface of the first epitaxial formation and inner surface of the second epitaxial formation.

8. The system of claim 7, wherein the semiconductor device processing system is further adapted to:

form an insulating region around and between the first fin and the second fin prior to depositing the conformal dielectric material, wherein an upper portion of the first fin and an upper portion of the second fin are above the insulating region.

9. The system of claim 7, wherein the semiconductor device processing system is adapted to etch the conformal dielectric material such that a top of the merged conformal dielectric layer between the inner surfaces of the first and second epitaxial formations is higher than a top of the conformal dielectric layer on the outer surfaces of the first and second epitaxial formations.

10. The system of claim 7, wherein the semiconductor device processing system is further adapted to:

form a third epitaxial formation on the first epitaxial formation; and

form a fourth epitaxial formation on the second epitaxial formation;

wherein the third and fourth epitaxial formations are not formed on the conformal dielectric layer.

11. The system of claim 7, wherein the semiconductor device processing system is adapted to deposit a material selected from nitrides and oxides as the conformal dielectric material.

12. The system of claim 7, wherein the semiconductor device processing system is adapted to deposit the conformal dielectric material by atomic layer deposition (ALD).