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Memory device comprising an electrically floating body transistor and methods of operating

  • US 10,529,853 B2
  • Filed: 08/20/2018
  • Issued: 01/07/2020
  • Est. Priority Date: 11/01/2016
  • Status: Active Grant
First Claim
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1. A semiconductor memory cell comprising:

  • a memory transistor comprising a bi-stable floating body transistor having a first floating body region and a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and

    an access device comprising a second body region;

    wherein said bi-stable floating body transistor and said access device are electrically connected in series;

    wherein said bi-stable floating body transistor further comprises a first gate region connected to a first terminal;

    wherein said access device further comprises a second gate region connected to a second terminal;

    wherein said access device further comprises a bit line region connected to a third terminal;

    wherein a first voltage level applied to said first terminal during write operations to both said first and second states is about the same;

    wherein a second voltage level applied to said second terminal during said write operations to both said first and second states is about the same; and

    wherein there is a time delay between when said first voltage level is triggered and when said second voltage level is triggered.

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