Memory device comprising an electrically floating body transistor and methods of operating

• US 10,529,853 B2
• Filed: 08/20/2018
• Issued: 01/07/2020
• Est. Priority Date: 11/01/2016
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Maheshwari, Dinesh, Widjaja, Yuniarto
• Primary Examiner(s): Shook, Daniel P
• Application Number:
  US16/105,579
• Publication Number:
  US 20190006516A1
• Time in Patent Office: 505 Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Claims

1. A semiconductor memory cell comprising:

a memory transistor comprising a bi-stable floating body transistor having a first floating body region and a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and

an access device comprising a second body region;

wherein said bi-stable floating body transistor and said access device are electrically connected in series;

wherein said bi-stable floating body transistor further comprises a first gate region connected to a first terminal;

wherein said access device further comprises a second gate region connected to a second terminal;

wherein said access device further comprises a bit line region connected to a third terminal;

wherein a first voltage level applied to said first terminal during write operations to both said first and second states is about the same;

wherein a second voltage level applied to said second terminal during said write operations to both said first and second states is about the same; and

wherein there is a time delay between when said first voltage level is triggered and when said second voltage level is triggered.

2. The semiconductor memory cell of claim 1, wherein a capacitance of said first floating body region is different from a capacitance of said second floating body region.

3. The semiconductor memory cell of claim 1, wherein a length of the first gate region is less than a length of the second gate region.

4. The semiconductor memory cell of claim 1, wherein a length of the first gate region is greater than a length of the second gate region.

5. The semiconductor memory cell of claim 1, wherein a volume of the first floating body region is smaller than a volume of the second body region.

6. The semiconductor memory cell of claim 1, wherein a capacitance of the first gate region is different from a capacitance of the second gate region.

7. The semiconductor memory cell of claim 1, further comprising at least one dummy gate region between said memory transistor and said access device.

8. The semiconductor memory cell of claim 7, wherein a work function of said dummy gate region is higher than a work function of said first gate region.

9. The semiconductor memory cell of claim 1, wherein a third voltage level is applied to said third terminal to write said first state, and a fourth voltage level is applied to said third terminal to write said second state.

10. The semiconductor memory cell of claim 1, wherein said semiconductor memory cell is a multi-port memory cell.

11. The semiconductor memory cell of claim 1 comprising a fin structure.

12. A method of operating a semiconductor memory cell having a bi-stable floating body transistor and an access transistor, wherein the bi-stable floating body transistor comprises a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states;

said method comprising;

applying a first voltage to said access transistor to turn on said access transistor; and

applying a second voltage to a gate region of said bi-stable floating body transistor, wherein there is a time delay between when said first voltage is triggered and when said second voltage is triggered.

13. The method of claim 12, wherein said access transistor further comprises a bit line region, and wherein a third voltage is applied to said bit line region of said access transistor to write said first state and a fourth voltage is applied to said bit line region of said access transistor to write said second state.

14. The method of claim 12, wherein said first voltage to turn on said access transistor is a negative voltage.

15. The method of claim 12, wherein said second voltage is a positive voltage.

16. The method of claim 13, wherein said third voltage is a positive voltage and wherein said fourth voltage is a negative voltage.

17. The method of claim 13, wherein applying a first voltage to turn on said access transistor passes said third voltage and fourth voltage to a drain region of said bi-stable floating body transistor.

18. The method of claim 13, wherein said first voltage is negative and said fourth voltage is negative, and wherein said first voltage is more negative than said fourth voltage.

19. The method of claim 12, wherein said semiconductor memory cell is a multi-port memory cell.

20. The method of claim 12, wherein said semiconductor memory cell comprises a fin structure.