Virtual negative bevel and methods of isolating adjacent devices

• US 10,529,884 B2
• Filed: 11/09/2017
• Issued: 01/07/2020
• Est. Priority Date: 11/09/2017
• Status: Active Grant

• Current Assignee: Lightspin Technologies Inc.
• Original Assignee: Lightspin Technologies Inc.
• Inventors: Harmon, Eric
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US15/808,605
• Publication Number:
  US 20190140128A1
• Time in Patent Office: 789 Days
• CPC Class Codes: H01L 27/14 including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation radiation-sensitive components structurally associated with one or more electric light sources only H01L31/14; couplings of light guides with optoelectronic elements G02B6/42
• CPC Class Codes: H01L 27/142 Energy conversion devices photovoltaic modules or arrays of single photovoltaic cells comprising bypass diodes integrated or directly associated with the devices H01L31/0443; photovoltaic modules composed of a plurality of thin film solar cells deposited on the same substrate H01L31/046
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 31/02027 for devices working in avalanche mode
• CPC Class Codes: H01L 31/035272 characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

This disclosure is directed to devices and systems and methods comprising virtual negative beveled facets including to isolate adjacent devices from one another. Aspects hereof are directed to integrated photon detectors or photodetector devices incorporating implant isolation mesas and resistors, and in particular to methods and structures for isolating such detectors or devices from neighboring detectors or devices.

Claims

1. A semiconductor device comprising:

a substrate layer;

a first semiconductor layer doped with a first dopant disposed above said substrate layer and a second semiconductor layer doped with a second dopant, the second semiconductor layer disposed on said first semiconductor layer, said first dopant having a first dopant type opposite to a second dopant type of said second dopant;

said first and second semiconductor layers being ion implanted with first ions in selected regions thereof, said first ions forming defined first implant isolated regions, wherein an unimplanted region is disposed between said first implant isolated regions;

a first contact disposed above said first implanted regions of said second semiconductor layer; and

a second contact disposed to contact said first semiconductor layer or said substrate layer;

wherein said second semiconductor layer is truncated, thereby isolating said semiconductor device from neighboring semiconductor devices; and

wherein the first implanted regions are implanted at negative bevel angles with respect to a planar bottom surface of said first semiconductor layer, said planar bottom surface proximal to said substrate layer, whereby said unimplanted region forms a virtual negative bevel mesa structure having angled side profiles.

2. The device of claim 1, wherein said truncated second semiconductor layer is formed by etching.

3. The device of claim 1, wherein said truncated second semiconductor layer is formed by implant isolation.

4. The semiconductor device of claim 1, wherein said second semiconductor layer is ion implanted with second ions to form defined second implanted regions in a portion of each first implanted region.

5. The semiconductor device of claim 4, wherein each second implanted region is disposed between said unimplanted region and said respective contact.

6. The semiconductor device of claim 5, wherein each said second implanted region forms a resistor and a portion of a bypass capacitor, the resistor and bypass capacitor in parallel electrically with each other.

7. The semiconductor device of claim 5, wherein said second implanted regions are insulating.

8. The semiconductor device of claim 7, further comprising a patterned metal or resistor layer disposed between each contact and said unimplanted region of said second semiconductor layer.

9. The semiconductor device of claim 4, wherein said first and second implanted regions in said second semiconductor layer form a guard ring.

10. The semiconductor device of claim 1, wherein said first semiconductor layer comprises an N−

material and said second semiconductor layer comprises a P++ material.

11. The semiconductor device of claim 1, wherein said first semiconductor layer comprises a P−

material and said second semiconductor layer comprises an N++ material.