Multi-wafer based light absorption apparatus and applications thereof

• US 10,529,886 B2
• Filed: 06/01/2018
• Issued: 01/07/2020
• Est. Priority Date: 07/24/2015
• Status: Active Grant

• Current Assignee: Artilux, Inc.
• Original Assignee: Artilux, Inc.
• Inventors: Cheng, Szu-Lin, Liu, Han-Din, Chen, Shu-Lu, Na, Yun-Chung, Chen, Hui-Wen
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US15/996,261
• Publication Number:
  US 20190140132A1
• Time in Patent Office: 585 Days
• CPC Class Codes: H01L 27/14629 Reflectors
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 31/02005 for device characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/02161 for devices characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/028 including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/0549 comprising spectrum splitting means, e.g. dichroic mirrors
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• CPC Class Codes: H01L 31/1812 including only AIVBIV alloys, e.g. SiGe
• CPC Class Codes: H01L 31/1892 methods involving the use of temporary, removable substrates
• CPC Class Codes: Y02E 10/52 PV systems with concentrators
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs'"'"' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.

Claims

1. A semiconductor structure comprising:

a first silicon wafer having a front side;

a photosensitive material layer deposited on the front side of the first silicon wafer, the photosensitive material layer including a number of Si_xGe_(1-x) layers, wherein 0≤

x<

1;

a passivation layer on top of the photosensitive material layer; and

a second silicon wafer having a front side,

wherein the first silicon wafer and the second silicon wafer are bonded together with the passivation layer facing the front side of the second silicon wafer.

2. The structure of claim 1, wherein, in the number of Si_xGe_(1-x) layers, an x value of one Si_xGe_(1-x) layer is different than another Si_xGe_(1-x) layer.

3. The structure of claim 1, wherein the passivation layer comprises a material also contained on top of the second silicon wafer.

4. The structure of claim 3, wherein the material also contained on top of the second silicon wafer comprises silicon.

5. The structure of claim 1, wherein the passivation layer comprises a semiconductor material that is not silicon-germanium based but exhibits a passivation effect to the photosensitive material layer.

6. The structure of claim 1, wherein the passivation layer comprises a semiconductor material that is lattice-matched to germanium.

7. The structure of claim 1, wherein the passivation layer is gallium arsenide.

8. The structure of claim 1, wherein the photosensitive material layer is doped to a predetermined doping profile suitable for a photodetector.

9. The structure of claim 1, wherein the passivation layer is doped by impurities.

10. The structure of claim 1, wherein the passivation layer and the second silicon wafer are doped by a same kind of dopant.

11. The structure of claim 10, wherein the dopant is N-type.

12. The structure of claim 1, wherein the front side of the first silicon wafer has been polished.

13. The structure of claim 1, wherein the first silicon wafer has been annealed.

14. The structure of claim 1, wherein the second silicon wafer has been patterned.

15. The structure of claim 1, further comprising:

an additional passivation layer on the front side of the second silicon wafer.

16. The structure of claim 1, wherein the first and second silicon wafers are bonded together by one or more of:

a dry wafer bonding, a wet wafer bonding, a chemical wafer bonding, or a plasma assisted wafer bonding.

17. The structure of claim 1, further comprising other portions of a photodetector fabricated on the second silicon wafer.

18. The structure of claim 1, further comprising a separation layer on the first silicon wafer.