Bit line structures for three-dimensional arrays with magnetic tunnel junction devices including an annular free magnetic layer and a planar reference magnetic layer

• US 10,529,915 B2
• Filed: 08/08/2018
• Issued: 01/07/2020
• Est. Priority Date: 03/23/2018
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Araki, Satoru
• Primary Examiner(s): Tobergte, Nicholas J
• Application Number:
  US16/059,016
• Publication Number:
  US 20190296222A1
• Time in Patent Office: 517 Days
• CPC Class Codes: G11C 11/155 with cylindrical configuration
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 2211/5615 Multilevel magnetic memory cell using non-magnetic non-conducting interlayer, e.g. MTJ
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: H01F 10/3259 Spin-exchange-coupled multilayers comprising at least a nanooxide layer [NOL], e.g. with a NOL spacer
• CPC Class Codes: H01F 10/329 Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

A Magnetic Tunnel Junction (MTJ) can include an annular structure and a planar reference magnetic layer disposed about the annular structure. The annular structure can include an annular non-magnetic layer disposed about an annular conductive layer, an annular free magnetic layer disposed about the annular non-magnetic layer, and an annular tunnel insulator disposed about the annular free magnetic layer. The planar reference magnetic layer can be separated from the free magnetic layer by the annular tunnel barrier layer.

Claims

1. A memory device comprising:

an array of Magnetic Tunnel Junction (MTJ) cells arranged in cell columns and cell rows in a plurality of cell levels, wherein the MTJ cells in corresponding cell column and cell row positions in the plurality of cell levels are coupled together in cell strings, each MTJ cell includes;

an annular structure including an annular tunnel insulator disposed about an annular free magnetic layer;

a planar reference magnetic layer disposed about the annular structure;

a planar non-magnetic insulator layer disposed on a first side of the planar reference magnetic layer and about the annular structure; and

another respective planar non-magnetic insulator layer disposed on a second side of the planar reference magnetic layer and about the annular structure.

2. The memory device of claim 1, wherein,

a magnetic field of the planar reference magnetic layer has a fixed polarization substantially perpendicular to a major planar orientation of the planar reference magnetic layer;

and

a magnetic field of the annular free magnetic layer has a polarization substantially perpendicular to the major planar orientation of the planar reference magnetic layer and selectively switchable between being substantially parallel and substantially antiparallel to the magnetic field of the planar reference layer.

3. The memory device of claim 2, wherein the magnetic field of the annular free magnetic layer is configured to switch to being substantially parallel to the magnetic field of the planar reference layer in response to a current flow in a first direction through the conductive annular layer and to switch to being substantially anti-parallel to the magnetic field of the planar reference layer in response to a current flow in a second direction through the conductive annular layer.

16. The memory device of claim 1, further comprising:

a plurality of bit lines, wherein respective bit lines are disposed on and electrically coupled to respective planar magnetic layers of respective cell levels; and

a plurality of select elements arranged in select columns and select rows, wherein respective selector elements are coupled to respective strings of MTJ cells in corresponding cell column and cell row positions.

17. The memory device of claim 1, wherein the annular structure further includes an annular non-magnetic layer disposed about an annular conductive layer, and the annular free magnetic layer disposed about the annular non-magnetic layer.

26. The memory device of claim 16, further comprising:

a plurality of blocks of the array of MTJ cells arranged in block columns and block rows.

27. The memory device of claim 26, further comprising:

a plurality of global bit lines, each global bit line coupled to a set of bit lines in a corresponding column of the plurality of blocks of the array of MTJ cells.

28. The memory device of claim 16, wherein the plurality of bit lines are peripherally disposed about the array of MTJ cells.

29. The memory device of claim 17, wherein the annular structure comprises a conical structure including a conical non-magnetic layer disposed about a conical portion of the conductive layer, a conical free magnetic layer disposed about the conical non-magnetic layer, and a conical tunnel barrier layer disposed about the conical free magnetic layer.

4. A device comprising:

a first plurality of annular structures, each annular structure including an annular tunnel insulator disposed about an annular free magnetic layer;

a first planar reference magnetic layer disposed about the first plurality of annular structures and separated from the free magnetic layers of the first plurality of annular structures by the annular tunnel barrier layers of the first plurality of annular structures;

a first non-magnetic insulator layer disposed about the first plurality of annular structures and on a first side of the first planar reference magnetic layer;

a second non-magnetic insulator layer disposed about the first plurality of annular structures and on a second side of the first planar reference magnetic layer;

a second plurality of annular structures axially aligned with respective ones the first plurality of annular structures;

a second planar reference magnetic layer disposed about the second plurality of annular structures and separated from the free magnetic layer of the second plurality of annular structures by the annular tunnel barrier layers of the second plurality of annular structures;

a third non-magnetic insulator layer disposed about the second plurality of annular structures and between the second non-magnetic insulator layer and a first side of the second planar reference magnetic layer; and

a fourth non-magnetic insulator layer disposed about the second plurality of annular structures and on a second side of the second planar reference magnetic layer.

5. The device of claim 4, wherein:

the first plurality of annular structures are arranged in columns and rows; and

the second plurality of annular structures are arranged in columns and rows, and axially aligned with respective ones the first plurality of annular structures.

18. The device of claim 4, wherein each annular structure further includes an annular non-magnetic layer disposed about an annular conductive layer, and the annular free magnetic layer disposed about the annular non-magnetic layer.

19. The device of claim 4, further comprising:

a first bit line coupled to the first planar reference magnetic layer; and

a second bit line coupled to the second planar reference magnetic layer.

30. The device of claim 19, further comprising:

a third plurality of annular structures;

a third planar reference magnetic layer disposed about the third plurality of annular structures and separated from the free magnetic layer of the third plurality of annular structures by the annular tunnel barrier layers of the third plurality of annular structures;

a fifth non-magnetic insulator layer disposed about the third plurality of annular structures and between the fourth non-magnetic insulator layer and a first side of the third planar reference magnetic layer;

a sixth non-magnetic insulator layer disposed about the third plurality of annular structures and on a second side of the third planar reference magnetic layer; and

a third bit line coupled to the third planar reference magnetic layer.

31. The device of claim 18, further comprising:

a non-magnetic metal layer disposed between the second non-magnetic insulator layer and the third non-magnetic insulator layer and between the first plurality of annular structures and the second plurality of annular structures.

32. The device of claim 18, further comprising:

an additional non-magnetic insulator layer disposed between the second non-magnetic insulator layer and the third non-magnetic insulator layer; and

a non-magnetic metal plug disposed between respective ones of the annular conductive layer of the first plurality of annular structures and the annular conductive layer of the second plurality of annular structures.

33. The device of claim 18, further comprising:

the plurality of annular structures arranged in columns and rows in the first and second planar reference magnetic layers; and

a plurality of insulator regions disposed in the first and second planar reference magnetic layers between a respective pair of columns of the plurality of annular structures.

6. A memory device comprising:

an array of Magnetic Tunnel Junction (MTJ) cells arranged in a plurality of cell levels coupled together in cell strings, the MTJ cells in each cell string include;

an annular structure including an annular tunnel insulator disposed about an annular free magnetic layer;

corresponding planar reference magnetic layers disposed about the annular structure and aligned with a corresponding ones of the plurality of portions of the free magnetic layer;

one or more planar non-magnetic insulator layers disposed on a first side of each of the plurality of planar reference magnetic layers and about the annular structure; and

one or more other planar non-magnetic insulator layers disposed on a second side of each of the plurality of planar reference magnetic layers and about the annular structure.

7. The memory device of claim 6, further comprising:

a plurality of blocks of the array of MTJ cells arranged in block columns and block rows.

8. The memory device of claim 7, further comprising:

a plurality of global bit lines, each global bit line coupled to a set of bit lines in a corresponding column of the plurality of blocks of the array of MTJ cells.

9. The memory device of claim 6, wherein the annular structure comprises a conical structure including a conical non-magnetic layer disposed about a conical portion of the conductive layer, a conical free magnetic layer disposed about the conical non-magnetic layer, and a conical tunnel barrier layer disposed about the conical free magnetic layer.

10. The memory device of claim 6, wherein,

a magnetic field of the planar reference magnetic layer has a fixed polarization substantially perpendicular to a major planar orientation of the planar reference magnetic layer;

and

a magnetic field of the annular free magnetic layer has a polarization substantially perpendicular to the major planar orientation of the planar reference magnetic layer and selectively switchable between being substantially parallel and substantially antiparallel to the magnetic field of the planar reference layer.

11. The memory device of claim 10, wherein the magnetic field of the annular free magnetic layer is configured to switch to being substantially parallel to the magnetic field of the planar reference layer in response to a current flow in a first direction through the conductive annular layer and to switch to being substantially anti-parallel to the magnetic field of the planar reference layer in response to a current flow in a second direction through the conductive annular layer.

20. The memory device of claim 6, wherein the MTJ cells are arranged in corresponding cell column and cell row positions in the plurality of cell levels.

21. The memory device of claim 20, wherein the annular structure further includes an annular non-magnetic layer disposed about an annular conductive layer, an annular free magnetic layer disposed about the annular non-magnetic layer, and wherein the annular free magnetic layer separated in each annular structure separated from each other by corresponding ones of a plurality of non-magnetic separator layers.

22. The memory device of claim 21, further comprising:

a plurality of bit lines, wherein respective bit lines are disposed on and electrically coupled to respective planar magnetic layers of respective cell levels; and

a plurality of select elements arranged in select columns and select rows, wherein respective selector elements are coupled to respective strings of cells in corresponding cell column and cell row positions.

34. The memory device of claim 22, wherein the plurality of bit lines are peripherally disposed about the array of MTJ cells.

12. A device comprising:

a plurality of annular structures, each annular structure including a first annular free magnetic layer and a second annular free magnetic layer separated by a non-magnetic separator layer, and an annular tunnel insulator disposed about the plurality of annular free magnetic layers and the non-magnetic separator layer;

a first planar reference magnetic layer disposed about the plurality of annular structures and aligned with the first annular free magnetic layer;

a first non-magnetic insulator layer disposed about the plurality of annular structures and on a first side of the first planar reference magnetic layer; and

a second non-magnetic insulator layer disposed about the plurality annular structures and on a second side of the first planar reference magnetic layers;

a second planar reference magnetic layer disposed about the plurality of annular structures and aligned with the second annular free magnetic layer;

a third non-magnetic insulator layer disposed about the plurality of annular structures and between the second non-magnetic insulator layer and a first side of the second planar reference magnetic layer;

a fourth non-magnetic insulator layer disposed about the plurality of annular structures and on a second side of the second planar reference magnetic layer.

13. The device of claim 12, wherein the plurality;

of annular structures are arranged in columns and rows.

14. The device of claim 12, further comprising:

a non-magnetic metal layer disposed between the second non-magnetic insulator layer and the third non-magnetic insulator layer.

15. The device of claim 12, further comprising:

the plurality of annular structures arranged in columns and rows in the first and second planar reference magnetic layers; and

a plurality of insulator regions disposed in the plurality of planar reference magnetic layers between a respective pair of columns of the plurality of annular structure.

23. The memory device of claim 12, wherein each annular structure further includes an annular non-magnetic layer disposed about an annular conductive layer, and wherein the first and second annular free magnetic layers are disposed about the annular non-magnetic.

24. The memory device of claim 23, wherein:

the first planar reference magnetic layer is separated from the free magnetic layers of the plurality of annular structures by the annular tunnel barrier layer of the plurality of annular structures and the first planar reference magnetic layer; and

the second planar reference magnetic layer is separated from the free magnetic layers of the plurality of annular structures by the annular tunnel barrier layers of the plurality of annular structures, and the second planar reference magnetic layer.

25. The memory device of claim 24, further comprising:

a first hit line coupled to the first planar reference magnetic layer; and

a second bit line coupled to the second planar reference magnetic layer.

35. The device of claim 23, further comprising:

the plurality of annular structures including a third annular free magnetic layer disposed about the annular non-magnetic layer, the third annular free magnetic layer separated from the second annular free magnetic layer by a second non-magnetic separator layer;

a third planar reference magnetic layer disposed about the plurality of annular structures and separated from the free magnetic layers of the plurality of annular structures by the annular tunnel barrier layers of the plurality of annular structures, and the third planar reference magnetic layer aligned with the third annular free magnetic layer;

a fifth non-magnetic insulator layer disposed about the plurality of annular structures and between the fourth non-magnetic insulator layer and a first side of the third planar reference magnetic layer;

a sixth non-magnetic insulator layer disposed about the plurality of annular structures and on a second side of the third planar reference magnetic layer; and

a third bit line coupled to the third planar reference magnetic layer.