Nonlinear bandwidth compression circuitry

• US 10,530,305 B2
• Filed: 02/05/2018
• Issued: 01/07/2020
• Est. Priority Date: 10/06/2017
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Folkmann, Andrew F., Khlat, Nadim, Retz, James M.
• Primary Examiner(s): Lee, Benny T
• Assistant Examiner(s): Rahman, Hafizur
• Application Number:
  US15/888,260
• Publication Number:
  US 20190109566A1
• Time in Patent Office: 701 Days
• Field of Search: 333 14
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H03F 2200/105 A non-specified detector of the power of a signal being used in an amplifying circuit
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2201/3215 To increase the output power or efficiency
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 2001/0408 with power amplifiers
• CPC Class Codes: H04B 2001/0425 with linearisation using predistortion
• CPC Class Codes: H04L 69/04 Protocols for data compression, e.g. ROHC
• CPC Class Codes: H04W 28/06 Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365
• CPC Class Codes: H04W 52/0209 in terminal devices terminal devices per se H04W88/02
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Nonlinear bandwidth compression circuitry is provided. In examples discussed herein, nonlinear bandwidth compression circuitry can be configured to modify predefined amplitude(s) of a predefined voltage waveform to generate modified amplitude(s) of a modified voltage waveform that is never less than the predefined amplitude(s) of the predefined voltage waveform. Thus, by providing the nonlinear bandwidth compression circuitry in an envelope tracking (ET) system to perform bandwidth compression, signal distortion(s) resulted from the bandwidth compression can be corrected (e.g., via digital pre-distortion). As such, the ET system can amplify a radio frequency (RF) signal having a signal modulation bandwidth exceeding a voltage modulation bandwidth limitation of the ET system, without degrading spectral performance of the RF signal.

Claims

1. Nonlinear bandwidth compression circuitry comprising:

an input node, an output node, and a reference node;

control circuitry comprising;

a reference input interface coupled to the reference node;

an output interface coupled to the output node;

one or more input interfaces; and

a feedback interface;

positive slew rate circuitry coupled to the control circuitry and comprising;

a delay path provided between the input node and the reference node; and

one or more combiners provided in parallel between the delay path and the one or more input interfaces in the control circuitry, respectively; and

negative slew rate circuitry coupled to the control circuitry and comprising feedback circuitry provided between the output interface and the feedback interface.

2. The nonlinear bandwidth compression circuitry of claim 1 wherein:

the input node is configured to receive a plurality of predefined voltage amplitudes;

the delay path is configured to delay the plurality of predefined voltage amplitudes by a defined delay to generate a plurality of reference voltage amplitudes at the reference node; and

the control circuitry is configured to receive the plurality of reference voltage amplitudes via the reference input interface and generate a plurality of modified voltage amplitudes greater than or equal to the plurality of reference voltage amplitudes, respectively, at the output interface.

3. The nonlinear bandwidth compression circuitry of claim 2 wherein the control circuitry is further configured to generate the plurality of modified voltage amplitudes at a reduced slew rate compared to the plurality of predefined voltage amplitudes.

4. The nonlinear bandwidth compression circuitry of claim 2 wherein:

the delay path comprises one or more delay circuits provided in series between the input node and the reference node and configured to generate one or more delta delays, respectively; and

the defined delay of the delay path equals approximately a sum of the one or more delta delays.

5. The nonlinear bandwidth compression circuitry of claim 4 wherein the delay path comprises at least two delay circuits configured to generate equal delta delays.

6. The nonlinear bandwidth compression circuitry of claim 4 wherein the delay path comprises at least two delay circuits configured to generate different delta delays.

7. The nonlinear bandwidth compression circuitry of claim 4 wherein:

the one or more delay circuits comprise one or more input ends and one or more output ends, respectively; and

the one or more combiners are provided in parallel between the one or more input ends and the one or more input interfaces, respectively.

8. The nonlinear bandwidth compression circuitry of claim 7 wherein:

the one or more input interfaces comprises a first input interface, one or more intermediate input interfaces succeeding to the first input interface, and a last input interface succeeding to the one or more intermediate input interfaces;

the one or more delay circuits comprise a first delay circuit, one or more intermediate delay circuits succeeding to the first delay circuit, and a last delay circuit succeeding to the one or more intermediate delay circuits, wherein;

a respective input end of the first delay circuit is coupled to the input node;

a respective input end of each of the one or more intermediate delay circuits and the last delay circuit is coupled to a respective output end of a preceding delay circuit among the one or more delay circuits; and

a respective output end of the last delay circuit is coupled to the reference node;

the one or more combiners comprise a first combiner, one or more intermediate combiners succeeding to the first combiner, and a last combiner succeeding to the one or more intermediate combiners, wherein;

the first combiner is coupled between the respective input end of the first delay circuit and the first input interface;

the one or more intermediate combiners are coupled between respective input nodes of the one or more intermediate delay circuits and the one or more intermediate input interfaces, respectively; and

the last combiner is coupled between a respective input interface of the last delay circuit and the last input interface.

9. The nonlinear bandwidth compression circuitry of claim 8 wherein:

the first delay circuit is configured to;

receive the plurality of predefined voltage amplitudes at the respective input end; and

output the plurality of predefined voltage amplitudes after a respective delta delay;

the one or more intermediate delay circuits are each configured to;

receive the plurality of predefined voltage amplitudes from an immediate preceding delay circuit among the one or more delay circuits; and

output the plurality of predefined voltage amplitudes after a first respective delta delay; and

the last delay circuit is configured to;

receive the plurality of predefined voltage amplitudes from the immediate preceding delay circuit among the one or more delay circuits; and

output the plurality of reference voltage amplitudes after a second respective delta delay.

10. The nonlinear bandwidth compression circuitry of claim 8 wherein each of the one or more combiners is configured to:

receive the plurality of predefined voltage amplitudes;

combine the plurality of predefined voltage amplitudes with a respective delta voltage to generate a plurality of adjusted predefined voltage amplitudes; and

provide the plurality of adjusted predefined voltage amplitudes to a coupled input interface among the one or more input interfaces.

11. The nonlinear bandwidth compression circuitry of claim 10 wherein:

the first combiner is configured to have the respective delta voltage equal to a predefined integer number multiplied by a voltage unit; and

each of the one or more intermediate combiners and the last combiner is configured to have the respective delta voltage that is one voltage unit higher than the respective delta voltage of an immediate preceding combiner among the one or more combiners.

12. The nonlinear bandwidth compression circuitry of claim 11 wherein the predefined integer number is determined based on a count of the one or more combiners.

13. The nonlinear bandwidth compression circuitry of claim 11 wherein the voltage unit equals a desired slew rate divided by a sample rate of a digital signal.

14. The nonlinear bandwidth compression circuitry of claim 10 wherein the feedback circuitry comprises:

a feedback delay circuit configured to receive and delay the plurality of modified voltage amplitudes by a respective delta delay; and

a feedback combiner configured to generate a plurality of feedback voltage amplitudes by reducing the plurality of modified voltage amplitudes by a respective delta voltage and provide the plurality of feedback voltage amplitudes to the feedback interface.

15. The nonlinear bandwidth compression circuitry of claim 14 wherein for each of the plurality of modified voltage amplitudes, the control circuitry is further configured to output a maximum voltage amplitude selected from each of the plurality of adjusted predefined voltage amplitudes received via the one or more input interfaces, each of the plurality of reference voltage amplitudes received via the reference input interface, and each of the plurality of feedback voltage amplitudes received via the feedback interface.

16. The nonlinear bandwidth compression circuitry of claim 1 further comprising:

input math transform circuitry provided between the input node and the delay path; and

output math transform circuitry provided between the output interface of the control circuitry and the output node.

17. The nonlinear bandwidth compression circuitry of claim 16 wherein:

the delay path comprises one or more delay circuits provided in series and configured to generate one or more delta delays, respectively;

the one or more delay circuits comprise one or more input ends and one or more output ends, respectively; and

the one or more combiners are provided in parallel between the one or more input ends and the one or more input interfaces, respectively.

18. The nonlinear bandwidth compression circuitry of claim 16 wherein the input math transform circuitry is a voltage-to-logarithm transform circuitry and the output math transform circuitry is a logarithm-to-voltage transform circuitry.

19. The nonlinear bandwidth compression circuitry of claim 16 wherein the input math transform circuitry is a square transform circuitry and the output math transform circuitry is a square-root transform circuitry.

20. The nonlinear bandwidth compression circuitry of claim 1 wherein the control circuitry is shared by the positive slew rate circuitry and the negative slew rate circuitry.