Envelope tracking amplifier circuit

• US 10,530,311 B2
• Filed: 10/03/2018
• Issued: 01/07/2020
• Est. Priority Date: 04/25/2017
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Khlat, Nadim, Gorisse, Philippe, Potts, Jeffrey D., Kay, Michael R.
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US16/150,556
• Publication Number:
  US 20190036493A1
• Time in Patent Office: 461 Days
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/18 by use of distributed coupling , i.e. distributed amplifiers distributed amplifiers using coupling networks with distributed constants H03F3/605
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/432 Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45522 the FBC comprising one or more potentiometers
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit

Abstract

Aspects disclosed in the detailed description include an envelope tracking (ET) amplifier circuit. The ET amplifier circuit includes ET tracker circuitry configured to provide an ET modulated voltage, which tracks an ET modulated target voltage, to an amplifier circuit(s) for amplifying a radio frequency (RF) signal. The ET amplifier circuit also includes fast switcher circuitry that is activated to provide an alternate current (AC) current to the amplifier circuit(s) when the RF signal includes a higher number of resource blocks (RBs). However, the fast switcher circuitry and its associated control circuitry may incur a processing delay that can cause the fast switcher circuitry to lag behind the ET modulated target voltage. As such, the ET amplifier circuit further includes timing adjustment circuitry to help compensate for the processing delay, thus helping to maintain efficiency of the ET tracker circuitry for improved performance of the ET amplifier circuit.

Claims

1. An envelope tracking (ET) amplifier circuit comprising:

an output node configured to provide an ET modulated voltage to at least one amplifier circuit for amplifying a radio frequency (RF) signal;

ET tracker circuitry comprising;

a tracker input configured to receive an ET modulated target voltage; and

a tracker output coupled to the output node and configured to output the ET modulated voltage tracking the ET modulated target voltage;

fast switcher circuitry coupled to the tracker output; and

a fast switcher controller configured to;

receive a time-advanced sense current indicative of an alternate current (AC) current sourced by the ET tracker circuitry and a determined timing advance relative to the ET modulated target voltage; and

activate the fast switcher circuitry to provide the AC current to the tracker output in response to the time-advanced sense current indicating that the AC current sourced by the ET tracker circuitry is greater than zero.

2. The ET amplifier circuit of claim 1 further comprising timing adjustment circuitry coupled between the tracker input and the fast switcher controller, the timing adjustment circuitry configured to:

generate the determined timing advance in the time-advanced sense current; and

delay the ET modulated target voltage by the determined timing advance.

3. The ET amplifier circuit of claim 2 wherein the determined timing advance is determined based at least on a processing delay associated with the fast switcher controller and the fast switcher circuitry.

4. The ET amplifier circuit of claim 2 wherein the timing adjustment circuitry comprises:

a programmable pole-zero amplifier coupled to the tracker input and configured to delay the ET modulated target voltage by the determined timing advance; and

a timing advance generator coupled between the programmable pole-zero amplifier and the fast switcher controller to generate the determined timing advance in the time-advanced sense current.

5. The ET amplifier circuit of claim 4 wherein the programmable pole-zero amplifier comprises:

a positive voltage input configured to receive a positive input voltage;

a negative voltage input configured to receive a negative input voltage;

a positive voltage output configured to output a positive output voltage;

a negative voltage output configured to output a negative output voltage;

a positive voltage feedback loop coupled from the positive voltage output to the positive voltage input; and

a negative voltage feedback loop coupled from the negative voltage output to the negative voltage input.

6. The ET amplifier circuit of claim 5 further comprising filter circuitry provided between the programmable pole-zero amplifier and the tracker input and configured to:

receive the positive output voltage and the negative output voltage from the positive voltage output and the negative voltage output, respectively; and

pass at least one of the positive output voltage and the negative output voltage to the tracker input as the ET modulated target voltage.

7. The ET amplifier circuit of claim 6 wherein the filter circuitry is provided by a low-pass filter circuitry.

8. The ET amplifier circuit of claim 5 wherein the programmable pole-zero amplifier further comprises:

positive resistor-capacitor (RC) circuitry configured to receive the positive input voltage and provide the positive input voltage to the positive voltage input;

negative RC circuitry configured to receive the negative input voltage and provide the negative input voltage to the negative voltage input;

positive feedback RC circuitry provided in the positive voltage feedback loop; and

negative feedback RC circuitry provided in the negative voltage feedback loop.

9. The ET amplifier circuit of claim 8 wherein the programmable pole-zero amplifier is configured to delay the ET modulated target voltage by the determined timing advance by adjusting a respective RC time constant of the positive feedback RC circuitry and the negative feedback RC circuitry.

10. The ET amplifier circuit of claim 8 wherein the positive RC circuitry and the negative RC circuitry are configured to collectively determine a zero output and a pole output of the programmable pole-zero amplifier.

11. The ET amplifier circuit of claim 10 wherein the timing advance generator is configured to receive the zero output of the programmable pole-zero amplifier and generate the determined timing advance in the time-advanced sense current based on the zero output.

12. The ET amplifier circuit of claim 11 wherein the zero output of the programmable pole-zero amplifier comprises a mirrored positive voltage proportional to the positive output voltage and a mirrored negative voltage proportional to the negative output voltage.

13. The ET amplifier circuit of claim 12 wherein the timing advance generator comprises a differential amplifier comprising:

a positive input end configured to receive the mirrored positive voltage;

a negative input end configured to receive the mirrored negative voltage; and

a voltage output end configured to output a differential output voltage based on the mirrored positive voltage and the mirrored negative voltage.

14. The ET amplifier circuit of claim 13 wherein:

the positive input end is coupled to a first resistor configured to induce a positive input current based on the mirrored positive voltage; and

the negative input end is coupled to a second resistor configured to induce a negative input current based on the mirrored negative voltage.

15. The ET amplifier circuit of claim 13 further comprising current summing circuitry coupled to the differential amplifier of the timing advance generator, the fast switcher controller, and the ET tracker circuitry.

16. The ET amplifier circuit of claim 15 wherein the current summing circuitry comprises a resistor coupled to the voltage output end of the differential amplifier and is configured to induce a differential current indicative of the determined timing advance based on the differential output voltage of the differential amplifier.

17. The ET amplifier circuit of claim 16 wherein the ET tracker circuitry is configured to provide a tracker sense current indicative of the AC current sourced by the ET tracker circuitry to the current summing circuitry.

18. The ET amplifier circuit of claim 17 wherein the ET tracker circuitry is further configured to:

generate the tracker sense current as a positive current greater than zero in response to the ET tracker circuitry sourcing the AC current to the output node; and

generate the tracker sense current as a negative current less than zero in response to the ET tracker circuitry sinking the AC current from the output node.

19. The ET amplifier circuit of claim 17 wherein the current summing circuitry is further configured to:

combine the differential current and the tracker sense current to generate the time-advanced sense current indicative of the AC current sourced by the ET tracker circuitry and the determined timing advance relative to the ET modulated target voltage; and

provide the time-advanced sense current to the fast switcher controller.

20. The ET amplifier circuit of claim 2 further comprising:

slow switcher circuitry configured to generate a direct current (DC) current; and

a slow switcher controller configured to activate the slow switcher circuitry to provide the DC current to the output node.