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Clock synchronization device

  • US 10,530,563 B2
  • Filed: 02/19/2018
  • Issued: 01/07/2020
  • Est. Priority Date: 06/23/2017
  • Status: Active Grant
First Claim
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1. A clock synchronizing circuit comprising:

  • a phase comparator comprising a first circuit having a first input configured to receive a data signal, the first circuit configured to detect edges of the data signal;

    a second circuit comprising a clock generator configured to generate a clock signal with adjustable frequency, wherein the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and wherein the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator;

    a first delay circuit having an input coupled to an output of the clock generator; and

    a second delay circuit having an input coupled to the first input of the first circuit, wherein the phase comparator comprises a second flip-flop having a data input and a clock input and a third flip-flop having a data input and a clock input, wherein the data input of each of the second and third flip-flops are coupled to an output of the first circuit, wherein the clock input of the second flip-flop is coupled to an output of the first delay circuit, wherein the clock input of the third flip-flop is coupled to an output of the second delay circuit, and wherein the outputs of the second and third flip-flops are coupled to the second circuit.

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