Clock synchronization device
First Claim
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1. A clock synchronizing circuit comprising:
- a phase comparator comprising a first circuit having a first input configured to receive a data signal, the first circuit configured to detect edges of the data signal;
a second circuit comprising a clock generator configured to generate a clock signal with adjustable frequency, wherein the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and wherein the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator;
a first delay circuit having an input coupled to an output of the clock generator; and
a second delay circuit having an input coupled to the first input of the first circuit, wherein the phase comparator comprises a second flip-flop having a data input and a clock input and a third flip-flop having a data input and a clock input, wherein the data input of each of the second and third flip-flops are coupled to an output of the first circuit, wherein the clock input of the second flip-flop is coupled to an output of the first delay circuit, wherein the clock input of the third flip-flop is coupled to an output of the second delay circuit, and wherein the outputs of the second and third flip-flops are coupled to the second circuit.
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Abstract
In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.
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Citations
22 Claims
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1. A clock synchronizing circuit comprising:
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a phase comparator comprising a first circuit having a first input configured to receive a data signal, the first circuit configured to detect edges of the data signal; a second circuit comprising a clock generator configured to generate a clock signal with adjustable frequency, wherein the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and wherein the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator; a first delay circuit having an input coupled to an output of the clock generator; and a second delay circuit having an input coupled to the first input of the first circuit, wherein the phase comparator comprises a second flip-flop having a data input and a clock input and a third flip-flop having a data input and a clock input, wherein the data input of each of the second and third flip-flops are coupled to an output of the first circuit, wherein the clock input of the second flip-flop is coupled to an output of the first delay circuit, wherein the clock input of the third flip-flop is coupled to an output of the second delay circuit, and wherein the outputs of the second and third flip-flops are coupled to the second circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of recovering a clock signal associated with a data signal, the method comprising:
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generating the clock signal; receiving the data signal at a clock input of a first flip-flop; detecting a first edge of the data signal; after detecting the first edge of the data signal, comparing an edge of the data signal with an edge of the clock signal; generating an up signal and a down signal based on the comparison by; receiving an output of the first flip-flop with a data input of a second flip-flop; receiving the output of the first flip-flop with a data input of a third flip-flop; receiving a delayed version of the data signal at a clock input of the third flip-flop; receiving a delayed version of the clock signal at a clock input of the second flip-flop; generating the up signal with an output of the first flip-flop; and generating the down signal with an output of the second flip-flop; adjusting a voltage of a charge pump circuit based on the up and down signals; and modifying a frequency of the clock signal based on the voltage of the charge pump circuit. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A circuit comprising:
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a clock generator configured to generate a clock signal; and a phase detector having an output coupled to the clock generator, the phase detector comprising; a first flip-flop having a clock input configured to receive an asynchronous data signal, a second flip-flop having a data input coupled to an output of the first flip-flop, and a clock input, a third flip-flop having a data input coupled to the output of the first flip-flop, and a clock input, a first delay circuit having an input coupled to an output of the clock generator and an output coupled to the clock input of the second flip-flop, a second delay circuit having an input coupled to the clock input of the first flip-flop and an output coupled to the clock input of the third flip-flop, wherein the phase detector is configured to; detect a first edge of the asynchronous data signal, after detecting the first edge of the asynchronous data signal, compare an edge of the asynchronous data signal with an edge of the clock signal, and modify a frequency of the clock signal based on the comparison. - View Dependent Claims (20, 21, 22)
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Specification