Transmitter with self-triggered transition equalizer

• US 10,530,616 B2
• Filed: 08/03/2016
• Issued: 01/07/2020
• Est. Priority Date: 09/29/2015
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Dong, Yikui Jen
• Primary Examiner(s): Tieu, Janice N
• Application Number:
  US15/761,938
• Publication Number:
  US 20180278440A1
• Time in Patent Office: 1,252 Days
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/03 Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• CPC Class Codes: H04L 25/03012 operating in the time domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

A transmitting device includes an output node, at least one driver circuit and transition equalization circuitry. The driver circuit drives an output data signal including a data transition onto the output node. The output of the transition equalization circuitry is coupled to the output node. The transition equalization circuitry begins to drive the output node at the data transition and ends driving of the output node a pre-determined delay after beginning to drive the output node. The transition equalization circuitry drives the output node by injecting current onto the output node if the data transition is a positive transition, and sinking current from the output node if the data transition is a negative transition.

Claims

1. A transmitting device, comprising:

an output node;

at least one driver circuit to drive an output data signal onto the output node, the output data signal having a plurality of data transitions; and

transition equalization circuitry having an output coupled to the output node, the transition equalization circuitry beginning to drive the output node at a data transition from the plurality of data transitions and ending driving of the output node a pre-determined delay after beginning to drive the output node,

wherein a drive strength of the transition equalizer circuitry varies depending on a magnitude of change of digital data in the plurality of data transitions.

2. The transmitting device of claim 1, wherein the transition equalization circuitry drives the output node by injecting current onto the output node responsive to the data transition being a positive transition, and sinking current from the output node responsive to the data transition being a negative transition.

3. The transmitting device of claim 1, wherein the pre-determined delay of the transition equalization circuitry is adjustable.

4. The transmitting device of claim 1, wherein a drive strength of the transition equalization circuitry is adjustable.

5. The transmitting device of claim 4, wherein transition equalization circuitry includes a plurality of circuit stages coupled in parallel to each other, the circuit stages being selectively enabled to adjust the drive strength.

6. The transmitting device of claim 1, wherein the driver circuit is a main driver of a finite impulse response driver.

7. The transmitting device of claim 1, further comprising:

a pre-driver circuit to generate at least one driver control signal,

wherein the driver circuit drives the output data signal based on the driver control signal, and

wherein the transition equalization circuitry triggers the driving of the output node responsive to the driver control signal.

8. The transmitting device of claim 7, wherein the transition equalization circuitry comprises:

a transition direction circuit to generate a data transition direction signal indicating whether the data transition is a positive transition or a negative transition based on the least one driver control signal;

a pulse generator circuit to generate a pulse signal having a signal pulse, a start of the signal pulse triggered by the least one driver control signal and the end of the signal pulse being a pre-determined delay after the start of the signal pulse; and

a transition adjuster circuit to inject current to or sink current from the output node based on the transition direction signal, the transition adjuster circuit being enabled or disabled by the pulse signal.

9. The transmitting device of claim 7, wherein the at least one driver control signal comprises a positive driver control signal and a negative driver control signal, and the transition equalization circuitry comprises:

a current injection circuit to inject current onto the output node responsive to the positive driver control signal indicating that the data transition is a positive data transition; and

a current sinking circuit to sink current from the output node responsive to the negative driver control signal indicating that the data transition is a negative data transition.

10. The transmitting device of claim 9, wherein the current injection circuit comprises a first resistor through which current is injected to the output node, and the current sinking circuit comprises a second resistor through which current is sunk from the output node.

11. The transmitting device of claim 9, wherein the current injection circuit comprises a first current source to source current to the output node, and the current sinking circuit comprises a current sink to sink current from the output node.

12. The transmitting device of claim 9, wherein:

the current injection circuit comprises;

a first inverter to invert the positive pre-driver signal into an inverted positive pre-driver signal;

a first switch controlled by an input of the first inverter; and

a second switch controlled by an output of the first inverter, the first switch and the second switch coupled in series between a first supply voltage and the output node; and

the current sinking circuit comprises;

a second inverter to invert the negative pre-driver signal into an inverted negative pre-driver signal;

a third switch controlled by an input of the second inverter; and

a fourth switch controlled by an output of the second inverter, the third switch and the fourth switch coupled in series between a second supply voltage and the output node.

13. The transmitting device of claim 7, wherein:

the at least one driver circuit comprises a first driver to drive the output signal onto the output node based on the at least one first driver control signal corresponding to a least significant bit of a multi-bit data symbol and a second driver to drive the output signal onto the output node based on at least one second driver control signal corresponding to a most significant bit of a multi-bit data symbol; and

wherein the transition equalization circuitry triggers the driving of the output node responsive to the at least one first driver control signal and the at least one second driver control signal.

14. The transmitting device of claim 1, wherein the drive strength of the transition equalizer circuitry varies by adjusting an amount of current injected into or sunk from the output node based on the magnitude of change of the digital data.

15. A method of operation in a transmitting device, comprising:

driving, with a line driver, an output data signal onto an output node, the output data signal having a plurality of data transitions; and

beginning to drive, with a transition equalizer circuit, the output node at a data transition from the plurality of data transitions; and

ending, by the transition equalizer circuit, driving of the output node a pre-determined delay after beginning to drive the output node,

wherein a drive strength of the transition equalizer circuit varies depending on a magnitude of change of digital data in the plurality of data transitions.

16. The method of claim 15, wherein beginning to drive the output node with the transition equalizer further comprises:

injecting current onto the output node responsive to the data transition being a positive transition; and

sinking current from the output node responsive to the data transition being a negative transition.

17. The method of claim 15, wherein driving the output data signal with a line driver comprises:

driving, by the line driver, the output data signal onto the output node based on the at least one first driver control signal corresponding to a least significant bit of a multi-bit data symbol and at least one second driver control signal corresponding to a most significant bit of a multi-bit data symbol; and

wherein the beginning to drive, with the transition equalizer circuit, the output node is triggered responsive to the at least one first driver control signal and the at least one second driver control signal.

18. The method of claim 15, further comprising:

generating, by a pre-driver circuit, at least one driver control signal;

driving, with the line driver, the output data signal based on the driver control signal; and

triggering, with the transition equalizer circuit, the adjusting at the output node responsive to the driver control signal.

19. The method of claim 15, wherein the drive strength of the transition equalizer circuit varies by adjusting an amount of current injected into or sunk from the output node based on the magnitude of change of the digital data.

20. A non-transitory computer readable storage medium storing a representation of a transmitting device, the transmitting device comprising:

at least one driver circuit to drive an output data signal onto an output node, the output data signal having a plurality of data transitions; and

transition equalization circuitry having an output coupled to the output node, the transition equalization circuitry beginning to drive the output node at a data transition from the plurality of data transitions and ending the driving a pre-determined delay after beginning to drive the output node,

wherein a drive strength of the transition equalizer circuitry varies depending on a magnitude of change of digital data in the plurality of data transitions.