Digital time domain readout circuit for bioFET sensor cascades

• US 10,533,966 B2
• Filed: 07/27/2017
• Issued: 01/14/2020
• Est. Priority Date: 07/27/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Jie, Huang, Jui-Cheng
• Primary Examiner(s): Soderquist, Arlen
• Application Number:
  US15/661,788
• Publication Number:
  US 20190033251A1
• Time in Patent Office: 901 Days
• Field of Search: 20440301, 422 8201- 8203
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82

Abstract

Various bioFET sensor readout circuits and their methods of operation are described. A readout circuit includes a plurality of logic gates coupled in cascade, a delay extractor, and a counting module. Each logic gate of the plurality of logic gates includes at least one bioFET sensor. The delay extractor is designed to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal. The counting module is designed to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.

Claims

1. A sensor readout circuit comprising:

a plurality of logic gates coupled in cascade, each logic gate comprising at least one bioFET sensor;

a delay extractor configured to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal; and

a counting module configured to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.

2. The sensor readout circuit of claim 1, further comprising a second plurality of logic gates coupled in cascade, wherein the reference signal is an output of the second plurality of logic gates.

3. The sensor readout circuit of claim 2, wherein an input of the plurality of logic gates coupled in cascade and an input of the second plurality of logic gates coupled in cascade are tied together to receive a same input signal.

4. The sensor readout circuit of claim 1, wherein the plurality of logic gates comprise a plurality of inverters.

5. The sensor readout circuit of claim 1, wherein the delay extractor comprises an XOR logic gate.

6. The sensor readout circuit of claim 1, wherein the counting module comprises:

an AND gate configured to receive the pulse-width signal and a clock signal and to output a pulse count signal; and

a digital counter configured to receive the pulse count signal and output the digital count.

7. The sensor readout circuit of claim 6, wherein the clock signal has a clock frequency between 800 MHz and 1.2 GHz.

8. The sensor readout circuit of claim 1, wherein the bioFET sensor is a dual-gate bioFET sensor.

9. The sensor readout circuit of claim 1, wherein the bioFET sensor in each logic gate comprises a functionalized surface exposed to a fluid within a microfluidic well or a microfluidic channel.

10. A sensor readout circuit comprising:

a plurality of inverters coupled in cascade, each inverter comprising at least one bioFET sensor, wherein an output of the plurality of inverters is fed back as an input to the plurality of inverters; and

a counting module configured to receive the output of the plurality of inverters and to output a digital count corresponding to a frequency of the output of the plurality of inverters.

11. The sensor readout circuit of claim 10, wherein the counting module comprises:

an AND gate configured to receive the output of the plurality of inverters and a clock signal and to output a count signal; and

a digital counter configured to receive the count signal and output the digital count.

12. The sensor readout circuit of claim 11, wherein the clock signal has a clock frequency between 50 kHz and 150 kHz.

13. The sensor readout circuit of claim 10, wherein the bioFET sensor is a dual-gate bioFET sensor.

14. The sensor readout circuit of claim 10, wherein the frequency of the output of the plurality of inverters is between 150 MHz and 250 MHz.

15. The sensor readout circuit of claim 10, wherein the bioFET sensor in each inverter includes a functionalized surface exposed to a fluid within a microfluidic well or a microfluidic channel.

16. A sensor readout circuit comprising:

a plurality of inverters coupled in cascade, each inverter comprising at least one bioFET sensor, wherein an output of the plurality of inverters is fed back as an input to the plurality of inverters;

a mixer configured to receive the output of the plurality of inverters and an oscillating reference signal and to generate a down-converted signal corresponding to a difference in an oscillation frequency between the output of the plurality of inverters and the oscillating reference signal; and

a counting module configured to receive the down-converted signal and to output a digital count corresponding to a frequency of the down-converted signal.

17. The sensor readout circuit of claim 16, further comprising a second plurality of inverters coupled in cascade, wherein an output of the second plurality of inverters is fed back as an input to the second plurality of inverters, and wherein the oscillating reference signal is the output of the second plurality of inverters.

18. The sensor readout circuit of claim 16, wherein the mixer comprises a flip flop with a clock input coupled to the oscillating reference signal.

19. The sensor readout circuit of claim 16, wherein the counting module comprises:

an AND gate configured to receive the down-converted signal and a clock signal and to output a count signal; and

a digital counter configured to receive the count signal and output the digital count.

20. The sensor readout circuit of claim 19, wherein the clock signal has a frequency between 5 KHz and 50 KHz.