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Digital time domain readout circuit for bioFET sensor cascades

  • US 10,533,966 B2
  • Filed: 07/27/2017
  • Issued: 01/14/2020
  • Est. Priority Date: 07/27/2017
  • Status: Active Grant
First Claim
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1. A sensor readout circuit comprising:

  • a plurality of logic gates coupled in cascade, each logic gate comprising at least one bioFET sensor;

    a delay extractor configured to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal; and

    a counting module configured to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.

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