Interconnect retimer enhancements

• US 10,534,034 B2
• Filed: 12/26/2013
• Issued: 01/14/2020
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Froelich, Daniel S., Das Sharma, Debendra
• Primary Examiner(s): Britt, Cynthia
• Assistant Examiner(s): Hossain, Sazzad
• Application Number:
  US15/039,515
• Publication Number:
  US 20160377679A1
• Time in Patent Office: 2,210 Days
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/3275 Fault detection or status indication
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/3688 for test execution, e.g. scheduling of test suites
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H04B 3/46 Monitoring; Testing

Abstract

A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

Claims

1. An apparatus comprising:

control logic to;

generate a test mode signal to include a test pattern and an error reporting sequence; and

transmitter logic to;

send the test mode signal on a serial, point-to-point link implemented on a physical transmission medium, wherein the link couples a first device to a second device, the link is compliant with a Peripheral Component Interconnect Express (PCIe)-based interconnect protocol, and the link is to comprise a retimer device and two sublinks coupled to the retimer, wherein the retimer is positioned between the first and second devices on the link, the test mode signal is to be sent on a particular one of the two sublinks, the test pattern is to be used by a receiving device to identify errors on the particular sublink, and the error reporting sequence comprises an ordered set based on the PCIe-based protocol and is to be encoded with error information to describe error status of sublinks in the two sublinks.

2. The apparatus of claim 1, wherein the test mode signal is sent within a loopback test mode and instances of the test mode signal are to be sent from the first device on the link over the retimer device to the second device and further sent from the second device over the retimer device back to the first device.

3. The apparatus of claim 1, further comprising receiver logic to receive at least one of the instances of the test mode signal from the second device on another one of the two sublinks of the link, wherein each instance of the test mode signal includes an instance of the test pattern and an instance of the error reporting sequence.

4. The apparatus of claim 3, further comprising error detection logic to determine one or more errors on the other sublink based on the instance of the test pattern.

5. The apparatus of claim 4, wherein errors are determined for a sublink based on an identification that an instance of the test pattern as included in a test mode signal received over the sublink deviates from an expected value for the test pattern.

6. The apparatus of claim 1, wherein the apparatus comprises the retimer.

7. The apparatus of claim 1, wherein the error reporting sequence comprises a plurality of segments and each segment describes error status of a respective one of the sublinks.

8. The apparatus of claim 7, wherein each segment describes one of a downstream channel and an upstream channel of a respective sublink.

9. The apparatus of claim 7, wherein each segment comprises one or more ordered sets and at least a portion of each ordered set in the one or more-ordered sets is to be encoded to identify error status of at least one of the sublinks.

10. The apparatus of claim 9, wherein each ordered set comprises a respective skip (SKP) ordered set.

11. The apparatus of claim 7, wherein the link comprises at least two extension devices and at least three sublinks, and the plurality of segments comprise at least five segments.

12. The apparatus of claim 1, wherein the error reporting sequence comprises error information for one or more of the sublinks of the link, and the error information includes one or more of:

a number of errors detected for one of the sublinks, a lane of the link on which an error appeared, and a location of errors detected in a received test pattern.

13. The apparatus of claim 1, wherein the test pattern comprises a predefined pattern to be regenerated at each sublink during a test.

14. The apparatus of claim 13, wherein the test pattern includes one or more ordered sets.

15. The apparatus of claim 14, wherein the one or more ordered sets comprise electrical idle exit sequence ordered set (EIEOS).

16. The apparatus of claim 1, wherein the control logic is to identify that the link is in a test mode, and the test mode signal is sent in accordance with the test mode.

17. A method comprising:

identifying that a serial, point-to-point link is to enter a test mode, wherein the link connects a first device to a second device and is implemented on a physical transmission medium, the link is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol, and the link comprises a retimer device positioned between the first and second devices on the link and two or more sublinks to couple the first and second devices to the retimer device, wherein the retimer device extends physical length of the link;

generating a test mode signal, wherein the test mode signal includes a test pattern and an error reporting sequence and the error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks, wherein the error reporting sequence comprises an ordered set based on the PCIe-based protocol; and

sending the test mode signal within the test mode on a particular one of the sublinks.

18. A system comprising:

a first device;

a second device communicatively coupled to the first device using a serial, point-to-point link, wherein the link comprises a plurality of physical lanes and is compliant with a Peripheral Component Interconnect Express (PCIe)-based interconnect protocol;

a retimer device included on the link, wherein the retimer device is positioned between the first and second devices on the link, and data is sent between the first and second devices on the link over the retimer device; and

test mode logic to;

send test mode signals within a test mode of the link, wherein the link comprises a plurality of sublinks connected to the retimer, each instance of the test mode signal corresponds to a test of a respective one of the sublinks and includes a test pattern and an error reporting sequence, the test pattern is to be used by a device receiving the test mode signal to identify errors on the corresponding sublink, and the error reporting sequence comprises an ordered set based on the PCIe-based protocol and is to be encoded with error information to describe error status determined for the sublinks.

19. The system of claim 18, wherein the test mode logic is further to:

receive test mode signals and assess the test pattern in the test mode signal to identify an error status of the sublink corresponding to the test mode signal.

20. The system of claim 19, wherein each of the retimer device and the first device include a respective instance of the test mode logic.

21. The system of claim 20, wherein the second device also includes an instance of the test mode logic.

22. The system of claim 18, further comprising reporting logic to record error status information for the plurality of sublinks determined from the test mode signals and included in the error reporting sequences in one or more registers corresponding to the link.

23. The system of claim 18, wherein the link includes at least two retimers positioned between the first and second devices.