Memory protocol

• US 10,534,540 B2
• Filed: 06/15/2016
• Issued: 01/14/2020
• Est. Priority Date: 06/06/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Walker, Robert M., Hall, Jr., James A.
• Primary Examiner(s): Thammavong, Prasith
• Application Number:
  US15/182,821
• Publication Number:
  US 20170351433A1
• Time in Patent Office: 1,308 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/261 Storage comprising a plurality of storage devices
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.

Claims

1. An apparatus, comprising:

a memory device comprising a number of block buffers; and

a controller coupled to the memory device configured to;

perform operations on the number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein a size of the block buffers is programmed by the block configuration register to match a size of a block in the memory device based on a buffer start address and a buffer end address, wherein the block configuration register includes target address registers that identify target addresses of data in the memory device associated with the operations, wherein the target address registers are paired with the buffer start address and the buffer end address for each of the number of block buffers, and wherein the operations are performed to read data from the number of block buffers that is retrieved from the target addresses in the memory device and write data to the number of block buffers on the memory device that is then written to the target addresses in the memory device.

2. The apparatus of claim 1, wherein the block configuration register includes a block buffer address register that includes the buffer start address, the buffer end address, and status information for each of the number of block buffers.

3. The apparatus of claim 1, wherein the block configuration register includes the target address register that includes a target address for each of the number of block buffers.

4. The apparatus of claim 1, wherein the block configuration register includes a status register that includes status information for each of the number of block buffers.

5. The apparatus of claim 1, wherein the controller is configured to receive a command from the host to program the block configuration register setting the buffer start address for each of the number of block buffers, the buffer end address for each of the number of block buffers, and a corresponding target address in an array of memory cells on the memory device.

6. The apparatus of claim 5, wherein the controller is configured to receive a command from the host to write data to the number of block buffers.

7. The apparatus of claim 6, wherein the controller is configured to receive a command from the host to commit a portion of data from the number of block buffers to the corresponding target address in the array of memory cells.

8. The apparatus of claim 5, wherein the controller is configured to receive a command from the host to read data from the number of block buffers.

9. The apparatus of claim 5, wherein the controller is configured to cause data from the corresponding target address in the array of memory cells to be written to the number of block buffers and to read the data from the number of block buffers based on the command from the host.

10. The apparatus of claim 5, wherein the controller is configured to cause status information for the number of block buffers to be updated upon completion of the commands.

11. A method comprising:

receiving one or more commands from a host at a block configuration register of a memory device that comprises a number of block buffers,

identifying target addresses of data in the memory device associated with operations based on one or more target address registers of the block configuration register, wherein the target address registers are paired with a buffer start address and a buffer end address for each of the number of block buffers; and

performing, at the memory device, operations on the number of the block buffers of the memory device based on the one or more commands received from the host, wherein a size of the block buffers is programmed by the block configuration register to match a size of a block in the memory device based on the buffer start address and the buffer end address, and wherein the operations comprise at least one of;

reading data from the number of block buffers, the data retrieved from the target addresses in the memory device;

or

writing data to the number of block buffers on the memory device and to the target addresses in the memory device.

12. The method of claim 11, wherein the block configuration register includes a block buffer address register that includes the buffer start address, the buffer end address, and status information for each of the number of block buffers.

13. The method of claim 11, wherein the block configuration register includes the target address register that includes a target address for each of the number of block buffers.

14. The method of claim 11, wherein the block configuration register includes a status register that includes status information for each of the number of block buffers.

15. The method of claim 11, further including receiving a command from the host to program the block configuration register by setting the buffer start address for each of the number of block buffers, the buffer end address for each of the number of block buffers, and a corresponding target address in an array of memory cells on the memory device.

16. The method of claim 15, further including receiving a command from the host to write data to the number of block buffers.

17. The method of claim 16, further including receiving a command from the host to commit a portion of data from the number of block buffers to the corresponding target address in the array of memory cells.

18. The method of claim 15, further including receiving a command from the host to read data from the number of block buffers.

19. The method of claim 15, further including causing data from the corresponding target address in the array of memory cells to be written to the number of block buffers and to read the data from the number of block buffers based on the command from the host.

20. A method comprising:

transmitting one or more commands from a host to a block configuration register of a memory device that comprises a number of block buffers;

communicating data between the number of block buffers of the block configuration register of the memory device and the host in response to the one or more commands, wherein the data is written to or read from the number of block buffers based at least in part on;

identification of target address of the data in the memory device associated with an operation based on one or more target address registers of the block configuration register, wherein the target address registers are paired with a buffer start address and a buffer end address for each of the number of block buffers; and

performance of the operations on the number of block buffers of the memory device based on the one or more commands transmitted from the host, wherein a size of the block buffers is programmable by the block configuration register to match a size of a block in the memory device based on the buffer start address and the buffer end address, wherein the operations comprise at least one of;

reading the data from the number of block buffers, the data received from the target addresses in the memory device;

or writing the data to the number of block buffers on the memory device and to the target address in the memory device.