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Memory protocol

  • US 10,534,540 B2
  • Filed: 06/15/2016
  • Issued: 01/14/2020
  • Est. Priority Date: 06/06/2016
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a memory device comprising a number of block buffers; and

    a controller coupled to the memory device configured to;

    perform operations on the number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein a size of the block buffers is programmed by the block configuration register to match a size of a block in the memory device based on a buffer start address and a buffer end address, wherein the block configuration register includes target address registers that identify target addresses of data in the memory device associated with the operations, wherein the target address registers are paired with the buffer start address and the buffer end address for each of the number of block buffers, and wherein the operations are performed to read data from the number of block buffers that is retrieved from the target addresses in the memory device and write data to the number of block buffers on the memory device that is then written to the target addresses in the memory device.

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