Semiconductor storage device

• US 10,535,391 B2
• Filed: 09/06/2018
• Issued: 01/14/2020
• Est. Priority Date: 03/13/2018
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Osada, Yoshiaki, Hatsuda, Kosuke
• Primary Examiner(s): Auduong, Gene N
• Application Number:
  US16/124,007
• Publication Number:
  US 20190287594A1
• Time in Patent Office: 495 Days
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 10/3286 Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy
• CPC Class Codes: H01F 10/329 Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.

Claims

1. A semiconductor storage device comprising:

a first memory cell and a second memory cell each of which includes a resistive change element and a selector;

a first conductor electrically coupled to a first end of the first memory cell;

a second conductor which electrically couples between a second end of the first memory cell and a first end of the second memory cell;

a third conductor electrically coupled to a second end of the second memory cell;

a first constant current source which is capable of coupling electrically to the first memory cell via the first conductor;

a second constant current source which is capable of coupling electrically to the second memory cell via the third conductor;

a first sense amplifier configured to read data from the first memory cell based on a current flowing from the first constant current source to the first memory cell; and

a second sense amplifier configured to read data from the second memory cell based on a current flowing from the second memory cell to the second constant current source.

2. The device of claim 1, further comprising

a first memory cell array and a second memory cell array each of which includes the first memory cell, the second memory cell, the first conductor, the second conductor, and the third conductor.

3. The device of claim 2, wherein

the first sense amplifier is configured to read data based on a current flowing from the first constant current source to the first memory cell in the first memory cell array or a current flowing from the first constant current source to the first memory cell in the second memory cell array, and

the second sense amplifier is configured to read data based on a current flowing from the second memory cell in the first memory cell array to the second constant current source or a current flowing from the second memory cell in the second memory cell array to the second constant current source.

4. The device of claim 3, wherein, during an operation of reading data from the first memory cell array and the second memory cell array, the second conductor in the first memory cell array and the second conductor in the second memory cell array are selected together.

5. The device of claim 3, wherein,

during an operation of reading data from the first memory cell array and the second memory cell array,

the first conductor in the first memory cell array and the third conductor in the second memory cell array are selected together, and

the third conductor in the first memory cell array and the first conductor in the second memory cell array are selected together.

6. The device of claim 1, further comprising:

a third memory cell and a fourth memory cell each of which includes the resistive change element and the selector;

a fourth conductor which electrically couples between a second end of the third memory cell and a first end of the fourth memory cell; and

a fifth conductor electrically coupled to a second end of the fourth memory cell, wherein

the third conductor electrically couples between the second end of the second, memory cell and a first end of the third memory cell,

the first constant current source is capable of coupling electrically to the third memory cell via the third conductor,

the second constant current source is capable of coupling electrically to the fourth memory cell via the fifth conductor,

the first sense amplifier is configured to read data from the third memory cell based on a current flowing from the first constant current source to the third memory cell, and

the second sense amplifier is configured to read data from the fourth memory cell based on a current flowing from the fourth memory cell to the second constant current source.

7. The device of claim 6, further comprising

a first memory cell array and a second memory cell array each of which includes the first memory cell, the second memory cell, the third memory cell, the fourth memory cell, the first conductor, the second conductor, the third conductor, the fourth conductor, and the fifth conductor.

8. The device of claim 7, wherein

the first sense amplifier is configured to read data based on a current flowing from the first constant current source to the first memory cell in the first memory cell array, a current flowing from the first constant current source to the third memory cell in the first memory cell array, a current flowing from the first constant current source to the first memory cell in the second memory cell array, or a current flowing from the first constant current source to the third memory cell in the second memory cell array, and

the second sense amplifier is configured to read data based on a current flowing from the second memory cell in the first memory cell array to the second constant current source, a current flowing from the fourth memory cell in the first memory cell array to the second constant current source, a current flowing from the second memory cell in the second memory cell array to the second constant current source, or a current flowing from the fourth memory cell in the second memory cell array to the second constant current source.

9. The device of claim 8, wherein,

during an operation of reading data from the first memory cell array and the second memory cell array,

the second conductor in the first memory cell array and the second conductor in the second memory cell array are selected together, and

the fourth conductor in the first memory cell array and the fourth conductor in the second memory cell array are selected together.

10. The device of claim 8, wherein,

during an operation of reading data from the first memory cell array and the second memory cell array,

the second conductor in the first memory cell array and the fourth conductor in the second memory cell array are selected together, and

the fourth conductor in the first memory cell array and the second conductor in the second memory cell array are selected together.

11. The device of claim 8, wherein

during an operation of reading data from the first memory cell array by the first sense amplifier and reading data from the second memory cell array by the second sense amplifier, one of the first conductor and the third conductor in the first memory cell array and one of the third conductor and the fifth conductor in the second memory cell array are selected together, and

during an operation of reading data from the second memory cell array by the first sense amplifier and reading data from the first memory cell array by the second sense amplifier, one of the third conductor and the fifth conductor in the first memory cell array and one of the first conductor and the third conductor in the second memory cell array are selected together.

12. The device of claim 1, further comprising:

a third memory cell and a fourth memory cell each of which includes the resistive change element and the selector;

a fourth conductor electrically coupled to a first end of the third memory cell;

a fifth conductor which electrically couples between a second end of the third memory cell and a first end of the fourth memory cell; and

a sixth conductor electrically coupled to a second end of the fourth memory cell, wherein

the first constant current source is capable of coupling electrically to the third memory cell via the fourth conductor,

the second constant current source is capable of coupling electrically to the fourth memory cell via the sixth conductor,

the first sense amplifier is configured to reads data from the third memory cell based on a current flowing from the first constant current source to the third memory cell, and

the second sense amplifier is configured to read data from the fourth memory cell based on a current flowing from the fourth memory cell to the second constant current source.

13. The device of claim 12, further comprising

a first memory cell array and a second memory cell array each of which includes the first memory cell, the second memory cell, the third memory cell, the fourth memory cell, the first conductor, the second conductor, the third conductor, the fourth conductor, the fifth conductor, and the sixth conductor.

14. The device of claim 13, wherein,

during an operation of reading data from the first memory cell array and the second memory cell array,

the second conductor in the first memory cell array and the second conductor in the second memory cell array are selected together, and

the fifth conductor in the first memory cell array and the fifth conductor in the second memory cell array are selected together.

15. The device of claim 13, wherein,

during an operation of reading data from the first memory cell array and the second memory cell array,

the second conductor in the first memory cell array and the fifth conductor in the second memory cell array are selected together, and

the fifth conductor in the first memory cell array and the second conductor in the second memory cell array are selected together.

16. The device of claim 13, wherein

during an operation of reading data from the first memory cell array by the first sense amplifier and reading data from the second memory cell array by the second sense amplifier, one of the first conductor and the fourth conductor in the first memory cell array and one of the third conductor and the sixth conductor in the second memory cell array are selected together, and

during an operation of reading data from the second memory cell array by the first sense amplifier and reading data from the first memory cell array by the second sense amplifier, one of the third conductor and the sixth conductor in the first memory cell array and one of the first conductor and the fourth conductor in the second memory cell array are selected together.

17. A semiconductor storage device comprising:

a first memory cell and a second memory cell each of which includes a resistive change element and a selector;

a first conductor electrically coupled to a first end of the first memory cell;

a second conductor which electrically couples between a second end of the first memory cell and a first end of the second memory cell;

a third conductor electrically coupled to a second end of the second memory cell;

a constant current source which is capable of coupling electrically to the first memory cell via the first conductor and is capable of coupling electrically to the second memory cell via the third conductor; and

a sense amplifier, wherein

the sense amplifier is configured to read data from the first memory cell based on a current flowing from the constant current source to the first memory cell via the first conductor, and

the sense amplifier is configured to read data from the second memory cell based on a current flowing from the constant current source to the second memory cell via the third conductor.

18. The device of claim 17, wherein

the resistive change element includes a first ferromagnetic material, a second ferromagnetic material, and a nonmagnetic material disposed between the first ferromagnetic material and the second ferromagnetic material, and

in the resistive change element in the first memory cell and the resistive change element in the second memory cell, the first ferromagnetic material, the nonmagnetic material, and the second ferromagnetic material are stacked in a same direction.

19. The device of claim 17, wherein

the resistive change element includes a first ferromagnetic material, a second ferromagnetic material, and a nonmagnetic material disposed between the first ferromagnetic material and the second ferromagnetic material, and

in the resistive change element in the first memory cell and the resistive change element in the second memory cell, the first ferromagnetic material, the nonmagnetic material, and the second ferromagnetic material are stacked in a opposite direction.

20. A semiconductor storage device comprising:

a first memory cell and a second memory cell each of which includes a resistive change element and a selector;

a first conductor electrically coupled to a first end of the first memory cell;

a second conductor which electrically couples between a second end of the first memory cell and a first end of the second memory cell;

a third conductor electrically coupled to a second end of the second memory cell;

a constant current source which is capable of coupling electrically to the first memory cell via the first conductor and is capable of coupling electrically to the second memory cell via the second conductor; and

a sense amplifier, wherein

the sense amplifier is configured to read data from the first memory cell based on a current flowing from the constant current source to the first memory cell via the first conductor, and

the sense amplifier is configured to read data from the second memory cell based on a current flowing from the constant current source to the second memory cell via the second conductor.