Dynamic bit-scan techniques for memory device programming

• US 10,535,401 B2
• Filed: 06/05/2018
• Issued: 01/14/2020
• Est. Priority Date: 06/05/2018
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Lin, Lei, Li, Zhuojie, Chin, Henry, Hsu, Cynthia
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US16/000,413
• Publication Number:
  US 20190371395A1
• Time in Patent Office: 588 Days
• Field of Search: 36518522
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Claims

1. A system comprising:

a memory die comprising a plurality of memory cells; and

a controller connected to the memory die, the controller configured to apply a plurality of programming pulses to the memory cells, and perform a variable state bitscan after each of multiple programming pulses, wherein the variable state bitscan repeatedly switches between an n-state bitscan and an m-state bitscan, where m>

n. and n>

0.

2. The system of claim 1, wherein the controller is further configured to repeatedly perform the n-state bitscan until all n states pass the n-state bitscan, and then switch to the m-state bitscan.

3. The system of claim 1, wherein the controller is further configured to repeatedly perform the m-state bitscan until all m states pass the m-state bitscan, and then switch to the n-state bitscan.

4. The system of claim 1, wherein the controller is further configured to:

perform the n-state bitscan by counting a number of memory cells that have not been programmed to a desired memory state for each of n memory states; and

perform the m-state bitscan by counting a number of memory cells that have not been programmed to a desired memory state for each of m memory states.

5. The system of claim 4, wherein the controller is further configured to collectively count memory cells for all memory states.

6. The system of claim 4, wherein the controller is further configured to separately count memory cells for each memory state.