Low power read operation for programmable resistive memories
First Claim
1. A programmable resistive memory, comprises:
- a primary cell including at least;
a selector controlled by a control signal, the selector having a first end and a second end, the second end being coupled to a first conductive line;
a capacitor selectively coupled to a second conductive line; and
a programmable resistive element (PRE) having a first end able to be coupled to the capacitor and a second end coupled to the first end of the selector; and
a reference cell including at least;
a reference selector controlled by the control signal, the reference selector having a first end and a second end, the second end being coupled to the first conductive line;
a reference capacitor selectively coupled to the second conductive line; and
a reference resistance element having a first end able to be coupled to the reference capacitor and a second end coupled to the first end of the reference selector,wherein a discharge time of the PRE relative to a discharge time of the reference resistance element is used to determine resistance of the PRE.
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Abstract
A programmable resistive memory has a plurality of programmable resistive devices (PRD) and at least one sensing circuit. The at least one of the programmable resistive device can include at least one programmable resistive element (PRE). The sensing circuit can include one PRD unit and a reference unit. Each unit has at least one capacitor to charge to a second supply voltage line and to discharge to the first supply voltage line through the PRE and the reference element, respectively. The capacitors are also coupled to comparators to monitor discharging voltages with respect to a reference voltage. By comparing the time difference when the comparators change their outputs, the magnitude of the PRE resistance with respect to the reference element resistance can be determined and converted into logic states.
375 Citations
19 Claims
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1. A programmable resistive memory, comprises:
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a primary cell including at least; a selector controlled by a control signal, the selector having a first end and a second end, the second end being coupled to a first conductive line; a capacitor selectively coupled to a second conductive line; and a programmable resistive element (PRE) having a first end able to be coupled to the capacitor and a second end coupled to the first end of the selector; and a reference cell including at least; a reference selector controlled by the control signal, the reference selector having a first end and a second end, the second end being coupled to the first conductive line; a reference capacitor selectively coupled to the second conductive line; and a reference resistance element having a first end able to be coupled to the reference capacitor and a second end coupled to the first end of the reference selector, wherein a discharge time of the PRE relative to a discharge time of the reference resistance element is used to determine resistance of the PRE. - View Dependent Claims (2, 3, 4, 7)
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5. A programmable resistive memory, comprises:
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a plurality of programmable resistive device (PRD) cells; and a time-based sensing circuit including at least; a selector controlled by a control signal, the selector having a first end and a second end, the second end being coupled to a first conductive line; a capacitor selectively coupled to a second conductive line; a programmable resistive element (PRE) having a first end coupled to the capacitor and a second end coupled to the first end of the selector; and a comparator coupled to the first end of the PRE, wherein the time-based sensing circuit using different discharge time to determine resistance of the PRE, wherein the programmable resistive element is an one-time programmable (OTP) element that comprises at least one of an anti-fuse, fuse or floating-gate device.
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6. A programmable resistive memory, comprises:
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a plurality of programmable resistive device (PRD) cells; and a time-based sensing circuit including at least; a selector controlled by a control signal, the selector having a first end and a second end, the second end being coupled to a first conductive line; a capacitor selectively coupled to a second conductive line; a programmable resistive element (PRE) having a first end coupled to the capacitor and a second end coupled to the first end of the selector; and a comparator coupled to the first end of the PRE, wherein the time-based sensing circuit using different discharge times to determine resistance of the PRE, wherein the programmable resistive element comprises at least one of RRAM or MRAM device.
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8. An electronic system, comprises:
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a processor; and a programmable resistive memory operatively connected to the processor, the programmable resistive memory includes at least a plurality of programmable resistive device (PRD) cells for providing data storage, each of the programmable resistive device cells comprising; a programmable resistive element (PRE) coupled to a first supply voltage line through a selector with an enable signal; and a time-base sensing circuit coupled to at least one PRD cell unit and a reference unit having a PRE and a reference resistor, respectively;
each of the PRD cell unit and the reference unit are coupled to capacitors that can be charged to a second supply voltage line and discharged through the PRE and the reference resistor, respectively, to the first supply voltage line;
the PRD cell unit and the reference unit are coupled to at least one comparator to change output logic state when the voltages are discharged to a reference voltage,wherein the capacitors in both units are charged to the second supply voltage approximately and discharged to the first supply voltage line by turning on the enable signal at the same time, and wherein the PRE resistance can be converted into logic state based on different discharge rates by the PRD cell unit and the reference unit. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for providing a programmable resistive memory, comprising:
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providing a plurality of programmable resistive device cells, at least one of the programmable resistive device cells include at least (i) a programmable resistive element coupled to a first supply voltage line through a selector with an enable signal; and
(ii) a time-base sensing circuit coupled to at least one PRD cell unit and a reference unit having a PRE and a reference resistor, respectively;
the PRD cell unit and the reference unit are coupled to at least one capacitor that can be charged to a second supply voltage line and discharged through the PRE and the reference resistor, respectively, to the first supply voltage line;
the PRD cell and the reference unit are coupled to at least one comparator, and wherein the comparator changes output logic states based on a comparison of the voltage discharged to a reference voltage;turning on the enable signal of the PRD unit and reference unit, after the capacitors are charged to the second supply voltage approximately, to discharge the capacitors through the PRE and reference element respectively; and converting the PRE resistance into logic states by the time difference of the comparator output changes. - View Dependent Claims (16, 17, 18, 19)
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Specification