Setting a default read signal based on error correction

• US 10,535,419 B2
• Filed: 03/06/2018
• Issued: 01/14/2020
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ratnam, Sampath K., Yanamanamanda, Satish K.
• Primary Examiner(s): Knapp, Justin R
• Application Number:
  US15/913,575
• Publication Number:
  US 20180197620A1
• Time in Patent Office: 679 Days
• Field of Search: None
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. Methods can include reading a page of data from the group of memory cells with a second discrete read signal different than the first discrete read signal and error correcting at least one codeword of the page of data as read with the second discrete read signal. One of the first and the second discrete read signals can be set as a default read signal based at least in part on the respective error corrections.

Claims

1. An apparatus, comprising:

a memory array; and

a controller coupled to the memory array and configured to;

read data from a group of memory cells of the memory array a plurality of times with a respective plurality of discrete read signals each having a different magnitude and each corresponding to a different trim set of a plurality of trim sets;

error correct the data read with the plurality of discrete read signals; and

set one of the plurality of discrete read signals as a default read signal based, at least in part, on the error correction.

2. The apparatus of claim 1, wherein the controller is configured to set the one of the plurality of discrete read signals as the default read signal that results in the fewest number of corrected errors based at least in part on the error correction.

3. The apparatus of claim 1, wherein the apparatus includes a plurality of dice, each including at least one memory array;

and

wherein the controller is configured to set the one of the plurality of discrete read signals as the default read signal for a number of the plurality of dice.

4. The apparatus of claim 1, wherein the group of memory cells includes a plurality of memory cells coupled by an access line and a plurality of data lines;

and

wherein the controller is configured to;

read the data from a portion of the group of memory cells that are coupled to a portion of the plurality of data lines; and

set the one of the plurality of discrete read signals as the default read signal for memory cells coupled to the portion of the plurality of data lines.

5. The apparatus of claim 1, wherein the memory array includes a plurality of strings of memory cells, wherein each string of memory cells of the array is coupled to a respective data line;

and

wherein the controller being configured to read the data from the group of memory cells comprises the controller being configured to sense at least one memory cell from the group of memory cells; and

wherein the controller being configured to set comprises the controller being configured to set the one of the plurality of discrete read signals as the default read signal for memory cells coupled to a same access line as the at least one memory cell from the group of memory cells.

6. The apparatus of claim 1, wherein the memory array includes a plurality of planes of memory cells;

and

wherein the controller being configured to read, error correct, and set comprises the controller being configured to;

read the data from a first plane of the memory array;

set the one of the plurality of discrete read signals as a default read signal for the first plane;

read data from a second plane of the memory array a plurality of times with the respective plurality of discrete read signals;

error correct the data read from the second plane with the plurality of discrete read signals; and

set one of the plurality of discrete read signals as a default read signal for the second plane based at least in part on the error correction.

7. The apparatus of claim 1, wherein the controller is configured to set a different default read signal for reading an upper page of data than for reading a lower page of data.

8. The apparatus of claim 1, wherein the memory array includes a plurality of blocks of memory cells;

and

wherein the controller being configured to read, error correct, and set comprises the controller being configured to;

read data from each of a portion of the plurality of blocks a plurality of times with the respective plurality of discrete read signals;

error correct the data read from the portion of the plurality of blocks with the plurality of discrete read signals; and

set as the default read signal the one of the plurality of discrete read signals that results in a fewest number of errors averaged across the portion of blocks as the default read signal.

9. The apparatus of claim 8, wherein the portion of blocks are topologically distributed throughout the memory array.

10. An apparatus, comprising:

a memory comprising units of memory; and

a controller coupled to the memory;

wherein the controller includes a plurality of trim sets each corresponding to a default read signal for at least one unit of the memory; and

wherein the controller is configured to;

read data from a group of memory cells within one of the units of memory with a plurality of discrete read signals; and

adjust one of the plurality of trim sets to set one of the plurality of discrete read signals as the default read signal for the one of the units of memory.

11. The apparatus of claim 10, wherein the controller being configured to adjust comprises the controller being configured to adjust the one of the plurality of trim sets to set the one of the plurality of discrete read signals as the default read signal for more than one of the units of memory.

12. The apparatus of claim 10, wherein the controller is configured to:

read data from a group of memory cells within a second one of the units of memory with the plurality of discrete read signals; and

adjust a second one of the plurality of trim sets to set a second one of the plurality of discrete read signals that results in the fewest number of errors during error correction of the data read from the group of memory cells within the second unit of memory as the default read signal for the second unit of memory.

13. The apparatus of claim 12, wherein the controller being configured to adjust the second one of the plurality of trim sets comprises the controller being configured to adjust the second one of the plurality of trim sets to set the second one of the plurality of discrete read signals as the default read signal for the second unit of memory and at least one other unit of memory.

14. The apparatus of claim 10, wherein the plurality of trims sets are fewer than the units of memory.

15. The apparatus of claim 10, wherein the plurality of trims sets are equal to the units of memory.

16. The apparatus of claim 10, wherein the units of memory comprise one of the group of units of memory including pages, blocks, planes, dice, channels, and logical units.

17. An apparatus, comprising:

a memory array; and

an error correction circuit coupled to the memory array, wherein the error correction circuit is configured to error correct data read from a group of memory cells of the memory array a plurality of times with a respective plurality of discrete read signals each having a different magnitude; and

a plurality of trim sets associated with the error correction circuit, wherein the a trim set among the plurality of trim sets corresponds to setting one of the plurality of discrete read signals as a default read signal based at least in part on the error correction.

18. The apparatus of claim 17, wherein the apparatus includes an error correction memory coupled to the error correction circuit, wherein the error correction memory is configured to store a number of errors corrected for each respective discrete read signal.

19. The apparatus of claim 18, wherein the trim set is associated with the error correction memory, and wherein the trim set being configured to set comprises the trim set being configured to set the one of the plurality of discrete read signals as the default read signal based at least in part on the number of errors corrected for each respective discrete read signal.

20. The apparatus of claim 18, wherein the apparatus includes the plurality of trim sets are further associated with the error correction memory.