Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures

• US 10,535,516 B2
• Filed: 02/01/2018
• Issued: 01/14/2020
• Est. Priority Date: 02/01/2018
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holdings B.V.
• Inventors: Kohen, David, Bhargava, Nupur, Tolle, John, D'Costa, Vijay
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US15/886,225
• Publication Number:
  US 20190237327A1
• Time in Patent Office: 712 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02452 including tin
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02656 Special treatments
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions

Abstract

A method for depositing a semiconductor structure on a surface of a substrate is disclosed. The method may include: depositing a first group IVA semiconductor layer over a surface of the substrate; contacting an exposed surface of the first group IVA semiconductor layer with a first gas comprising a first chloride gas; and depositing a second group IVA semiconductor layer over a surface of the first group IVA semiconductor layer. Related semiconductor structures are also disclosed.

Claims

1. A method for depositing a semiconductor structure on a surface of a substrate, the method comprising:

depositing a first group IVA semiconductor layer, comprising silicon germanium (Si_1-xGe_x), over a surface of the substrate;

contacting an exposed surface of the first group IVA semiconductor layer with a first gas comprising a first chloride gas;

depositing a second group IVA semiconductor layer, comprising silicon, over a surface of the first group IVA semiconductor layer; and

forming an interface region between the first group IVA semiconductor layer and the second group IVA semiconductor layer, wherein the interface region comprises a graded composition between having silicon germanium (Si_1-xGe_x) wherein x equals 0.3 proximate the first group IVA semiconductor layer and having silicon germanium (Si_1-xGe_x) wherein x equals 0 proximate the second group IVA semiconductor layer.

2. The method of claim 1, wherein the first gas further comprises a first group IVA gas.

3. The method of claim 2, wherein the first group IVA gas comprises at least one of dichlorosilane (DCS), dichlorosilane, trichlorosilane, tetrachlorosilane, hexachlorosilane, silane, or germane.

4. The method of claim 2, wherein the flow rate ratio of the first chloride gas in relation to the first group IVA gas is less than 2:

1.

5. The method of claim 2, wherein the contacting the exposed surface of the first group IVA semiconductor layer with the first gas results in substantially no net deposition of material.

6. The method of claim 1, wherein the surface of the substrate comprises a silicon surface.

7. The method of claim 1, wherein the first group IVA semiconductor layer has a germanium composition (x) equal to or greater than 0.30.

8. The method of claim 1, wherein the first chloride gas comprises at least one of hydrochloric acid (HCl), or chlorine (Cl₂).

9. The method of claim 1, wherein contacting an exposed surface of the first group IVA semiconductor layer with the first gas further comprises, contacting the exposed surface for a time period of less than 60 seconds.

10. The method of claim 1, further comprising contacting an exposed surface of the second group IVA semiconductor layer with a second gas comprising a second chloride gas.

11. The method of claim 10, wherein the second gas further comprises a second group IVA gas.

12. The method of claim 1, wherein a thickness of the interface region is less than 30 Angstroms.

13. The method of claim 12, wherein the thickness of the interface region is less than 15 Angstroms.

14. The method of claim 1, wherein a deposition cycle of the method comprises the depositing the first group IVA semiconductor layer, the contacting the exposed surface of the first group IVA semiconductor layer with the first gas, and the depositing the second group IVA semiconductor layer, and wherein the method further comprises repeating the deposition cycle one or more times.

15. The method of claim 14, further comprising forming a plurality of interface regions, each of the interface regions having a thickness of less than 15 Angstroms.

16. The method of claim 1, further comprising heating the substrate to a substrate temperature of less than 700°

C.

17. A semiconductor structure deposited according to the method of claim 1.

18. A semiconductor structure comprising:

a silicon substrate;

a first silicon germanium (Si_1-xGe_x) layer disposed over a surface of the silicon substrate;

a first silicon layer disposed over the first silicon germanium (Si_1-xGe_x) layer; and

a first interface region disposed directly between the first silicon germanium (Si_1-xGe_x) layer and the first silicon layer, wherein the interface region comprises a graded composition between having silicon germanium (Si_1-xGe_x) wherein x equals 0.3 proximate the first silicon germanium (Si_1-xGe_x) layer and having silicon germanium (Si_1-xGe_x) wherein x equals 0 proximate the first silicon layer.

19. The semiconductor structure of claim 18, further comprising:

a second silicon germanium (Si_1-xGe_x) layer disposed over the first silicon layer;

a second silicon layer disposed over the second silicon germanium (Si_1-xGe_x) layer; and

a second interface region disposed directly between the second silicon germanium (Si_1-xGe_x) layer and the second silicon layer;

wherein the second interface region has a thickness of less than 15 Angstroms.

20. The semiconductor structure of claim 19, further comprising:

a third silicon germanium (Si_1-xGe_x) layer disposed over the second silicon layer;

a third silicon layer disposed over the third silicon germanium (Si_1-xGe_x) layer; and

a third interface layer region disposed directly between the third silicon germanium (Si_1-xGe_x) layer and the third silicon layer;

wherein the third interface region has a thickness of less than 15 Angstroms.