Methods and structures for forming uniform fins when using hardmask patterns

• US 10,535,567 B2
• Filed: 04/23/2019
• Issued: 01/14/2020
• Est. Priority Date: 12/19/2017
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Xu, Peng, Cheng, Kangguo, Mignot, Yann, Lee, Choonghyun
• Primary Examiner(s): Ngo, Ngan V
• Application Number:
  US16/391,990
• Publication Number:
  US 20190252262A1
• Time in Patent Office: 266 Days
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 : using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

Claims

1. A semiconductor device comprising:

a plurality of fins on a substrate, wherein each of the plurality of fins has the same or substantially the same critical dimension in an active fin region;

a dielectric layer formed on the substrate and on and around each of the plurality of fins in a region below the active fin region; and

a plurality of dummy fins formed on the substrate;

wherein each of the plurality of dummy fins is positioned adjacent respective outermost fins of the plurality of fins, and is covered by the dielectric layer in the region below the active fin region; and

wherein the respective outermost fins each comprise a different critical dimension from an adjacent inner fin in the region below the active fin region.

2. The semiconductor device according to claim 1, wherein a height of each of the plurality of dummy fins is less than a height of the dielectric layer.

3. The semiconductor device according to claim 1, wherein a critical dimension of each of the plurality of dummy fins is less than the critical dimensions of each of the plurality of fins in the active fin region.

4. The semiconductor device according to claim 1, wherein a critical dimension of each of the plurality of dummy fins is less than the critical dimensions of each of the plurality of fins in the region below the active fin region.

5. The semiconductor device according to claim 1, wherein a critical dimension of each of the respective outermost fins of the plurality of fins in the active fin region is different than a critical dimension of each of the respective outermost fins of the plurality of fins in the region below the active fin region.

6. The semiconductor device according to claim 5, wherein the critical dimension of each of the respective outermost fins of the plurality of fins in the active fin region is less than the critical dimension of each of the respective outermost fins of the plurality of fins in the region below the active fin region.

7. The semiconductor device according to claim 5, wherein the adjacent inner fin is positioned between the respective outermost fins of the plurality of fins and has the same critical dimension in the active fin region and in the region below the active fin region.

8. The semiconductor device according to claim 1, further comprising a gate structure disposed on and around the plurality of fins.

9. The semiconductor device according to claim 8, wherein the gate structure is disposed on the dielectric layer.

10. The semiconductor device according to claim 8, wherein the gate structure comprises a dielectric layer and at least one conductive material.

11. A semiconductor device comprising:

a plurality of fins on a substrate, wherein each of the plurality of tins has the same or substantially the same critical dimension in an active fin region;

a dielectric layer formed on the substrate and on and around each of the plurality of fins in a region below the active fin region; and

a plurality of dummy fins formed on the substrate;

wherein each of the plurality of dummy fins is positioned adjacent respective outermost fins of the plurality of fins, and is covered by the dielectric layer in the region below the active fin region; and

wherein a critical dimension of each of the respective outermost fins of the plurality of fins in the active fin region is different than a critical dimension of each of the respective outermost fins of the plurality of fins in the region below the active fin region.

12. The semiconductor device according to claim 11, wherein a height of each of the plurality of dummy fins is less than a height of the dielectric layer.

13. The semiconductor device according to claim 11, wherein a critical dimension of each of the plurality of dummy fins is less than the critical dimensions of each of the plurality of fins in the active fin region.

14. The semiconductor device according to claim 11, wherein a critical dimension of each of the plurality of dummy fins is less than critical dimensions of each of the plurality of fins in the region below the active fin region.

15. The semiconductor device according to claim 11, wherein the critical dimension of each of the respective outermost fins of the plurality of fins in the active fin region is less than the critical dimension of each of the respective outermost fins of the plurality of fins in the region below the active fin region.

16. The semiconductor device according to claim 11, wherein a fin of the plurality fins positioned between the respective outermost fins of the plurality of fins has the same critical dimension in the active fin region and in the region below the active fin region.

17. The semiconductor device according to claim 11, further comprising a gate structure disposed on and around the plurality of fins.

18. The semiconductor device according to claim 17, wherein the gate structure is disposed on the dielectric layer.

19. The semiconductor device according to claim 17, wherein the gate structure comprises a dielectric layer and at least one conductive material.

20. The semiconductor device according to claim 11, wherein the respective outermost fins each comprise a greater critical dimension than a critical dimension of an adjacent inner fin in the region below the active fin region.