Vertical memory device including common source line structure

• US 10,535,599 B2
• Filed: 12/05/2017
• Issued: 01/14/2020
• Est. Priority Date: 01/28/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kim, Kwang-Soo
• Primary Examiner(s): Williams, Alexander O
• Application Number:
  US15/831,498
• Publication Number:
  US 20180102316A1
• Time in Patent Office: 770 Days
• Field of Search: 257774, 257324, 257326, 257773
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Claims

1. An integrated circuit (IC) device comprising:

a peripheral circuit on a substrate;

a semiconductor layer on the peripheral circuit;

a memory cell array region on the semiconductor layer and overlapping the peripheral circuit in a vertical direction, the memory cell array region comprising a plurality of memory cell arrays and a common source line tab region between adjacent two of the plurality of memory cell arrays;

a plurality of word lines that extend on the semiconductor layer, parallel to a main surface of the substrate, and are included in each of the plurality of memory cell arrays and separated from one another in a first direction perpendicular to the main surface of the substrate;

a plurality of channel regions that extend on the semiconductor layer in the first direction, passing through the plurality of word lines;

a plurality of bit line contact pads that are on the plurality of channel regions to contact the plurality of channel regions;

a plurality of bit lines that extend in a region separated from the common source line tab region, in a second direction parallel to the main surface of the substrate and contact a plurality of bit line contact pads;

a common source line that partially fills a word line cut region, the word line cut region extending in a third direction on a side of the plurality of word lines, the third direction being parallel to the main surface of the substrate and intersecting the second direction, the common source line having a height from a top surface of the semiconductor layer lower than that of the plurality of channel regions; and

at least one common source via contact that contacts an upper surface of the common source line in the common source line tab region and extends from the upper surface of the common source line in a direction away from the substrate.

2. The IC device of claim 1, wherein the IC device further comprises a pair of string select lines that extend parallel to the plurality of word lines on the plurality of word lines,

the plurality of channel regions extend through the plurality of word lines and the pair of string select lines, and

the plurality of channel regions each comprises a doped channel region in a region facing one of the pair of string select lines, the doped channel region being locally doped at a doping concentration higher than that of other region of each of the plurality of channel regions.

3. The IC device of claim 2, wherein the common source line has a sidewall facing the pair of string select lines.

4. The IC device of claim 2, wherein a level of an upper surface of the common source line is lower than a level of a lower surface of one of the pair of string select lines that is closest to the substrate.

5. The IC device of claim 2, wherein the IC device further comprises a word line cut region buried insulating layer that covers the common source line in the word line cut region, and

the word line cut region buried insulating layer has a sidewall facing the pair of string select lines.

6. The IC device of claim 1, wherein the IC device further comprises:

an insulating spacer that covers both sidewalls of the common source line in the word line cut region; and

a word line cut region buried insulating layer that covers the common source line and the insulating spacer in the word line cut region,

wherein a width of the word line cut region buried insulating layer in the second direction is greater than a width of the common source line in the second direction.

7. The IC device of claim 1, wherein the IC device further comprises a word line cut region buried insulating layer that covers the common source line in the word line cut region, and

the at least one common source via contact is surrounded by the word line cut region buried insulating layer in the word line cut region.

8. The IC device of claim 1, wherein a distance from the substrate to an upper surface of the common source via contact is greater than a distance from the substrate to an upper surface of one of the plurality of bit lines.