Chip package having die structures of different heights and method of forming same

• US 10,535,633 B2
• Filed: 04/30/2018
• Issued: 01/14/2020
• Est. Priority Date: 07/02/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wei, Wen-Hsin, Hu, Hsien-Pin, Hou, Shang-Yun
• Primary Examiner(s): Kim, Tong-Ho
• Application Number:
  US15/966,873
• Publication Number:
  US 20180254260A1
• Time in Patent Office: 624 Days
• Field of Search: 257773
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08235 the bonding area connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/182 : Disposition

Abstract

Structures and formation methods of a chip package are provided. The chip package includes a substrate, a first chip stack attached to the substrate, and a second chip stack attached to the substrate. The first chip stack and the second chip stack being attached to a same side of the substrate. The chip package further includes a molding compound layer surrounding the first chip stack and the second chip stack. The molding compound layer covers a topmost surface of the first chip stack. A topmost surface of the molding compound layer is substantially coplanar with a topmost surface of the second chip stack.

Claims

1. A package comprising:

a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface;

a first chip stack bonded to the first surface of the substrate;

a second chip stack bonded to the first surface of the substrate adjacent the first chip stack, the second chip stack being higher than the first chip stack; and

a molding compound layer extending along a topmost surface of the first chip stack, the topmost surface of the first chip stack being a farthest surface of the first chip stack from the substrate.

2. The package of claim 1, further comprising an underfill layer interposed between the substrate and the molding compound layer.

3. The package of claim 2, wherein a topmost surface of the underfill layer is above a bottommost surface of the first chip stack and a bottommost surface of the second chip stack.

4. The package of claim 1, wherein a topmost surface of the molding compound layer is substantially coplanar with a topmost surface of the second chip stack.

5. The package of claim 1, further comprising a redistribution structure on the second surface of the substrate, the redistribution structure being electrically coupled to the first chip stack and the second chip stack through the substrate.

6. The package of claim 1, wherein the substrate comprises at least one of a passive device and an active device.

7. The package of claim 1, wherein the second chip stack comprises a first integrated circuit die bonded to a second integrated circuit die, a first bond pad of the first integrated circuit die being in physical contact with a second bond pad of the second integrated circuit die.

8. A package comprising:

a substrate;

a first chip stack bonded to the substrate;

a second chip stack bonded to the substrate;

an underfill layer extending between the first chip stack and the substrate and between the second chip stack and the substrate, at least a portion of the underfill layer extending along sidewalls of the first chip stack and along sidewalls of the second chip stack; and

a package layer over the underfill layer, the package layer extending along a topmost surface of the first chip stack, an interface between the underfill layer and the package layer being above a bottommost surface of the first chip stack and below the topmost surface of the first chip stack.

9. The package of claim 8, wherein the first chip stack comprises:

a plurality of integrated circuit dies; and

an encapsulant extending along sidewalls of the plurality of integrated circuit dies and across the interface between the underfill layer and package layer.

10. The package of claim 9, wherein the encapsulant extends along and physically contacts a topmost surface of at least one integrated circuit die of the plurality of integrated circuit dies.

11. The package of claim 8, wherein the second chip stack comprises:

a first integrated circuit die, the first integrated circuit die comprising a first bond pad embedded into a first insulating layer; and

a second integrated circuit die bonded to the first integrated circuit die, the second integrated circuit die comprising a second bond pad embedded into a second insulating layer, the first insulating layer being in physical contact with the second insulating layer, the first bond pad being in physical contact with the second bond pad.

12. The package of claim 8, wherein a topmost surface of the second chip stack is substantially level with a topmost surface of the package layer.

13. The package of claim 8, further comprising a redistribution structure in electrical contact with the substrate, the substrate being interposed between the first chip stack and the redistribution structure.

14. A package comprising:

an interposer substrate, the interposer substrate comprising at least one of a passive device and an active device, the interposer substrate having a first surface and a second surface opposite the first surface;

a first chip structure attached to the first surface of the interposer substrate, wherein the first chip structure comprises a first integrated circuit die bonded to a second integrated circuit die, a first insulating layer on a first side of the first integrated circuit die being in physical contact with a second insulating layer on a second side of the second integrated circuit die;

a redistribution structure on the second surface of the interposer substrate; and

a molding compound layer surrounding the first chip structure, a topmost surface of the molding compound layer being substantially level with a topmost surface of the first chip structure.

15. The package of claim 14, further comprising a second chip structure attached to the first surface of the interposer substrate, wherein the first chip structure has a greater height than the second chip structure.

16. The package of claim 15, wherein the molding compound layer extends along sidewalls of the second chip structure and covers a topmost surface of the second chip structure.

17. The package of claim 15, further comprising an underfill layer surrounding the first chip structure and the second chip structure, an interface between the underfill layer and the molding compound layer being above a bottommost surface of the first chip structure and a bottommost surface of the second chip structure.

18. The package of claim 15, wherein the second chip structure comprises:

a stack of integrated circuit dies; and

an encapsulant extending along a sidewall of the stack of integrated circuit dies, the molding compound layer extending along a sidewall of the encapsulant.

19. The package of claim 14, further comprising a plurality of connectors bonded to the redistribution structure, the redistribution structure being interposed between the second surface of the interposer substrate and the plurality of connectors.

20. The package of claim 14, further comprising:

a first bond pad embedded into the first insulating layer; and

a second bond pad embedded into the second insulating layer, the first bond pad being in physical contact with the second bond pad.