System and method for the fluidic assembly of micro-LEDs utilizing negative pressure

• US 10,535,640 B2
• Filed: 08/31/2017
• Issued: 01/14/2020
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: Elux Inc.
• Original Assignee: Elux Inc.
• Inventors: Lee, Jong-Jan, Schuele, Paul J.
• Primary Examiner(s): Ellis, Suezu
• Application Number:
  US15/691,976
• Publication Number:
  US 20180012873A1
• Time in Patent Office: 866 Days
• CPC Class Codes: G02F 1/133603 with LEDs
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32055 being circular or elliptic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82104 using screen printing
• CPC Class Codes: H01L 2224/8284 Sintering
• CPC Class Codes: H01L 2224/83011 Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/83085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2224/83194 Lateral distribution of the layer connectors
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/83815 Reflow soldering
• CPC Class Codes: H01L 2224/92224 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

Abstract

An emissive panel and associated assembly method are provided. The method provides an emissive substrate having an insulating layer with a top surface and a back surface, and a dielectric layer overlying the insulating layer patterned to form a plurality of wells. Each well has a bottom surface formed on the insulating layer top surface with a first electrical interface electrically connected to a first conductive pressure channel (CPC). The CPCs are each made up of a pressure via with sidewalls formed between the well bottom surface and the insulating layer back surface. A metal layer coats the sidewalls, and a medium flow passage formed interior to the metal layer. The method uses negative pressure through the CPCs to help capture emissive elements in a liquid flow deposition process.

Claims

1. An emissive panel comprising:

an insulating layer comprising a top surface and a back surface;

a dielectric layer overlying the insulating layer top surface, patterned to form a first plurality of wells, each well comprising a bottom surface formed on an exposed region of the insulating layer top surface, well sidewalls formed in the dielectric layer, a first electrical interface formed on the well bottom surface, and a first electrically conductive pressure channel formed between the first electrical interface and the insulating layer back surface;

a control matrix comprising an electrically conductive first matrix of traces formed on a surface selected from a surface group consisting of the insulating layer top surface and the insulating layer bottom surface, and wherein an electrically conductive second matrix of traces is formed on an unselected surface from the surface group, where each first electrically conductive pressure channel is electrically connected to the first matrix;

a first plurality of surface mount emissive elements populating the wells, each emissive element comprising;

a top surface overlying a corresponding well bottom surface;

a bottom surface; and

,

a first electrical contact formed on the emissive element top surface and connected to a corresponding well first electrical interface.

2. The emissive panel of claim 1 wherein each emissive element further comprises a post connected to, and extending from the emissive element bottom surface.

3. The emissive panel of claim 1 further comprising:

a second electrical interface formed on each well bottom surface;

intralevel traces connecting each second matrix trace to corresponding second electrical interfaces; and

,

wherein each emissive element further comprises a second electrical contact formed on the emissive element top surface, connected to a corresponding well second electrical interface.

4. The emissive panel of claim 1 wherein each electrically conductive pressure channel comprises:

a pressure via with sidewalls formed between the well bottom surface and the insulating layer back surface;

a metal layer coating the sidewalls; and

,

a medium flow passage formed interior to the metal layer.

5. The emissive panel of claim 4 wherein each pressure via has a minimum cross-sectional area;

and,

wherein the medium flow passage has a minimum cross-sectional area greater than 50% of the pressure via minimum cross-sectional area.

6. The emissive panel of claim 4 wherein each pressure via has a cross-sectional area to pass a medium selected from the group consisting of a gas or a liquid.

7. The emissive panel of claim 1 further comprising:

solder flux residue residing on the emissive element top surfaces and in the first electrically conductive pressure channels.

8. The emissive panel of claim 1 further comprising:

a color modifier overlying the emissive elements.

9. The emissive panel of claim 8 further comprising:

a liquid crystal display (LCD) panel overlying a top surface of the color modifier.

10. The emissive panel of claim 1 wherein the surface mount emissive elements are light emitting diodes (LEDs).

11. The emissive panel of claim 1 wherein the insulating layer is a printed circuit board (PCB).

12. The emissive panel of claim 1 wherein the first plurality of wells formed in the dielectric layer have a cross-sectional circular shape.

13. An emissive panel comprising:

an insulating layer comprising a top surface and a back surface;

a dielectric layer overlying the insulating layer top surface, patterned to form a first plurality of wells, each well comprising a bottom surface formed on an exposed region of the insulating layer top surface, well sidewalls formed in the dielectric layer, a first electrical interface and a second electrical interface formed on the well bottom surface, and a first conductive pressure channel formed between the first electrical interface and the insulating layer back surface;

a control matrix comprising a conductive first matrix of traces formed on a surface selected from a surface group consisting of the insulating layer top surface and the insulating layer bottom surface, and wherein a conductive second matrix of traces is formed on an unselected surface from the surface group, where each first conductive pressure channel is operatively connected to the first matrix;

a first plurality of surface mount emissive elements populating the wells, each emissive element comprising;

a top surface overlying a corresponding well bottom surface;

a bottom surface;

a first electrical contact formed on the emissive element top surface and connected to a corresponding well first electrical interface;

a second electrical contact formed on the emissive element top surface and connected to a corresponding well second electrical interface; and

,

wherein the control matrix further comprises intralevel traces connecting each second matrix trace to corresponding second electrical interfaces.

14. The emissive panel of claim 13 wherein each emissive element further comprises a post connected to, and extending from the emissive element bottom surface.

15. The emissive panel of claim 13 wherein each conductive pressure channel comprises:

a pressure via with sidewalls formed between the well bottom surface and the insulating layer back surface;

a metal layer coating the sidewalls; and

,

a medium flow passage formed interior to the metal layer.

16. The emissive panel of claim 15 wherein each pressure via has a minimum cross-sectional area;

and,

wherein the medium flow passage has a minimum cross-sectional area greater than 50% of the pressure via minimum cross-sectional area.

17. The emissive panel of claim 15 wherein each pressure via has a cross-sectional area to pass a medium selected from the group consisting of a gas or a liquid.

18. The emissive panel of claim 13 further comprising:

solder flux residue residing on the emissive element top surfaces and in the first conductive pressure channels.

19. The emissive panel of claim 13 further comprising:

a color modifier overlying the emissive elements.

20. The emissive panel of claim 19 further comprising:

a liquid crystal display (LCD) panel overlying a top surface of the color modifier.

21. The emissive panel of claim 13 wherein the surface mount emissive elements are light emitting diodes (LEDs).

22. The emissive panel of claim 13 wherein the insulating layer is a printed circuit board (PCB).

23. The emissive panel of claim 13 wherein the first plurality of wells formed in the dielectric layer have a cross-sectional circular shape.