High density vertical thyristor memory cell array with improved isolation

• US 10,535,657 B2
• Filed: 08/22/2017
• Issued: 01/14/2020
• Est. Priority Date: 08/22/2016
• Status: Active Grant

• Current Assignee: Tc Lab, Inc.
• Original Assignee: Tc Lab, Inc.
• Inventors: Luan, Harry, Axelrad, Valery
• Primary Examiner(s): Malsawma, Lex H
• Assistant Examiner(s): Swan, Gardner W. S.
• Application Number:
  US15/683,760
• Publication Number:
  US 20180053766A1
• Time in Patent Office: 875 Days
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: H01L 27/0817 Thyristors only
• CPC Class Codes: H01L 27/1027 Thyristors
• CPC Class Codes: H01L 29/66371 structurally associated with another device, e.g. built-in diode making integrated circuits H01L21/82
• CPC Class Codes: H10B 10/10 SRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 53/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

Claims

1. An integrated circuit having an array of vertical thyristor memory cells in a semiconductor substrate, each vertical thyristor memory cell separated from other vertical thyristor memory cells by isolation regions, each isolation region comprising:

a trench extending parallel to a surface of the semiconductor substrate and separating at least two pairs of vertical memory cells;

an electrically isolating core in the trench; and

insulating material enclosing the electrically isolating core in the trench, the insulating material and electrically isolating core occupying an entirety of the trench;

whereby the isolation region electrically isolates the vertical thyristor memory cell from interference by operations of neighboring memory cells.

2. The integrated circuit of claim 1, wherein the electrically isolating core comprises an air tube along the trench.

3. The integrated circuit of claim 1, wherein the insulating material comprises silicon dioxide.

4. An integrated circuit having a semiconductor substrate, comprising:

a first thyristor having a vertically stacked P-conductivity type anode, N-conductivity type base, P-conductivity type base, and N-conductivity cathode provided by the semiconductor substrate;

a second thyristor having a vertically stacked P-conductivity type anode, N-conductivity type base, P-conductivity type base, and N-conductivity cathode provided by the semiconductor substrate; and

an isolation region separating the first thyristor from the second thyristor, the isolation region including

a trench extending into the semiconductor substrate below a junction region between the P-conductivity type base and the N-conductivity cathode of each of the first and second thyristors, the trench extending parallel to a surface of the semiconductor substrate and separating at least two pairs of vertical thyristor memory cells;

an electrically isolating core; and

insulating material surrounding the electrically isolating core in the trench, the insulating material and electrically isolating core occupying an entirely of the trench;

whereby the isolation region electrically isolates the first and second thyristors from interference by operation of the other thyristor.

5. The integrated circuit of claim 4, wherein the electrically isolating core comprises an air tube along the trench.

6. The integrated circuit of claim 4, wherein the insulating material comprises silicon dioxide.