Cell boundary structure for embedded memory

• US 10,535,671 B2
• Filed: 07/09/2019
• Issued: 01/14/2020
• Est. Priority Date: 11/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Ming Chyi, Liu, Shih-Chang, Chen, Sheng-Chieh, Chang, Yu-Hsing
• Primary Examiner(s): Ahmed, Selim U
• Application Number:
  US16/506,207
• Publication Number:
  US 20190333921A1
• Time in Patent Office: 189 Days
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region

Abstract

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Claims

1. An integrated circuit (IC) comprising:

a substrate;

an isolation structure extending into a top surface of the substrate and comprising a dielectric material;

a plurality of dummy layers stacked on the isolation structure, wherein the dummy layers are different materials and collectively define a dummy sidewall;

a seal structure on the isolation structure and sealing the dummy sidewall, wherein a width of the seal structure decreases continuously from a bottom of the dummy sidewall to a top of the dummy sidewall; and

a pair of semiconductor devices on the substrate, wherein the isolation structure electrically separates the semiconductor devices from each other, and wherein the seal structure is level with the semiconductor devices.

2. The IC according to claim 1, wherein a cross-sectional profile of the seal structure is right-trapezoid shaped.

3. The IC according to claim 1, wherein the width of the seal structure is greater than zero at a topmost surface of the seal structure.

4. The IC according to claim 1, wherein the seal structure shares a common material with at least one of the dummy layers.

5. The IC according to claim 1, wherein the plurality of dummy layers comprises an oxide-nitride-oxide (ONO) layer and a doped polysilicon layer overlying the ONO layer.

6. The IC according to claim 1, wherein the seal structure comprises a metal.

7. An integrated circuit (IC) comprising:

a substrate;

an isolation structure extending into a top surface of the substrate and comprising a dielectric material;

a boundary structure overlying the isolation structure, wherein the boundary structure has a boundary sidewall; and

a spacer structure overlying the isolation structure and lining the boundary sidewall, wherein the spacer structure and the isolation structure define a common sidewall on an opposite side of the spacer structure as the boundary structure, and wherein the common sidewall is smooth from top to bottom.

8. The IC according to claim 7, wherein a top edge of the common sidewall is level with a top surface of the boundary structure, and wherein a bottom edge of the common sidewall is recessed relative to a bottom surface of the boundary structure.

9. The IC according to claim 7, wherein the common sidewall is a single, first material from the isolation structure to a top edge of the common sidewall, and wherein the common sidewall is a single, second material from the spacer structure to a bottom edge of the common sidewall.

10. The IC according to claim 7, further comprising:

a semiconductor device on the substrate, wherein the common sidewall slants downwards towards the semiconductor device.

11. The IC according to claim 7, wherein the spacer structure consists essentially of a single material.

12. The IC according to claim 7, wherein the boundary sidewall is substantially vertical and comprises multiple different materials.

13. The IC according to claim 7, wherein the boundary sidewall is at a first angle relative to the top surface of the substrate, wherein the common sidewall is at a second angle relative to the top surface of the substrate, and wherein the second angle is less than the first angle.

14. The IC according to claim 7, further comprising:

a second boundary structure on the isolation structure, wherein the spacer structure is between the boundary structure and the second boundary structure, and wherein the spacer structure is spaced from the second boundary structure.

15. The IC according to claim 7, wherein a cross-sectional profile of the spacer structure is right-trapezoid shaped.

16. An integrated circuit (IC) comprising:

a substrate;

a trench isolation structure extending into a top surface of the substrate and comprising a dielectric material;

a nitride layer overlying the trench isolation structure;

a doped polysilicon layer overlying the nitride layer; and

a polysilicon spacer on the trench isolation structure and covering a sidewall of the doped polysilicon layer and a sidewall of the nitride layer.

17. The IC according to claim 16, wherein the polysilicon spacer has a spacer sidewall on an opposite side of the polysilicon spacer as the doped polysilicon layer, and wherein the spacer sidewall is at an acute angle relative to the top surface of the substrate.

18. The IC according to claim 16, further comprising:

an oxide layer between the doped polysilicon layer and the nitride layer, wherein the polysilicon spacer is on a sidewall of the oxide layer.

19. The IC according to claim 18, further comprising:

a memory device on the substrate and comprising a gate electrode and a gate dielectric layer, wherein the gate electrode and the gate dielectric layer directly contact at a first interface, and wherein the oxide layer and the doped polysilicon layer directly contact at a second interface level with the first interface.

20. The IC according to claim 16, further comprising:

an interlayer dielectric (ILD) layer wrapping around a top corner of the polysilicon spacer from a sidewall of the polysilicon spacer to a top surface of the polysilicon spacer, and wherein the ILD layer extends laterally from the top surface of the polysilicon spacer to a top surface of the doped polysilicon layer.