Strained nanowire CMOS device and method of forming

• US 10,535,732 B2
• Filed: 11/20/2017
• Issued: 01/14/2020
• Est. Priority Date: 10/07/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Cheng-Yi, Chiang, Hung-Li, Yang, Yu-Lin, Yeh, Chih Chieh, Yeo, Yee-Chia, Liu, Chi-Wen
• Primary Examiner(s): Maruf, Sheikh
• Application Number:
  US15/817,601
• Publication Number:
  US 20180090570A1
• Time in Patent Office: 785 Days
• Field of Search: 257401, 257369, 257192, 257 76, 257407, 257E2706, 257288, 257273, 257347, 257E2142, 438283
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Claims

1. A semiconductor device comprising:

a substrate;

first source/drain regions and a first channel region interposed between the first source/drain regions, the first source/drain regions and the first channel region comprising alternating layers of first epitaxial layers and second epitaxial layers, the first epitaxial layers and the second epitaxial layers extending continuously between the first source/drain regions;

second source/drain regions and a second channel region interposed between the second source/drain regions, the second source/drain regions comprising alternating layers of the first epitaxial layers and the second epitaxial layers, the second channel region comprising the second epitaxial layers wherein a gap in the first epitaxial layers exists between the second source/drain regions;

a first gate electrode extending over the first channel region; and

a second gate electrode extending over the second channel region.

2. The semiconductor device of claim 1, wherein a width of the second epitaxial layers in the first channel region is less than a width of the first epitaxial layers in the first channel region in a direction perpendicular to current flow through the first channel region.

3. The semiconductor device of claim 1, wherein edges of the second epitaxial layers in the second channel region are rounded in a direction perpendicular to current flow through the second channel region.

4. The semiconductor device of claim 1, wherein the first source/drain regions comprise a third epitaxial layer extending along sidewalls of the first epitaxial layers and the second epitaxial layers.

5. The semiconductor device of claim 4, wherein the second source/drain regions comprise a fourth epitaxial layer extending along sidewalls of the first epitaxial layers and the second epitaxial layers, wherein the third epitaxial layer and the fourth epitaxial layer are formed of different materials.

6. The semiconductor device of claim 1, further comprising a first gate dielectric over the second channel region, the first gate dielectric extending between adjacent ones of the second epitaxial layers in the second channel region.

7. The semiconductor device of claim 1, wherein the first gate electrode and the second gate electrode is a same continuous gate electrode.

8. A semiconductor device comprising:

a substrate;

first source/drain regions and a first channel region interposed between the first source/drain regions, the first source/drain regions and the first channel region comprising alternating layers of first epitaxial layers and second epitaxial layers, the first epitaxial layers in the first channel region having a greater width than the second epitaxial layers in the first channel region in a direction perpendicular to current flow through the first channel region;

second source/drain regions and a second channel region interposed between the second source/drain regions, the second source/drain regions and the second channel region comprising alternating layers of the first epitaxial layers and the second epitaxial layers, the second epitaxial layers in the second channel region having a greater width than the first epitaxial layers in the second channel region in a direction perpendicular to current flow through the second channel region; and

a gate electrode extending over the first epitaxial layers and the second epitaxial layers in the first channel region and the second channel region.

9. The semiconductor device of claim 8, wherein a bottommost layer of the first epitaxial layers in the second channel region is removed.

10. The semiconductor device of claim 8, further comprising a gate dielectric interposed between the gate electrode and the second channel region, wherein the gate dielectric extends between a bottommost second epitaxial layer in the second channel region and the substrate.

11. The semiconductor device of claim 8, wherein sidewalls of the second epitaxial layers in the first channel region are concave in a direction perpendicular to current flow through the first channel region.

12. The semiconductor device of claim 11, wherein sidewalls of the first epitaxial layers in the second channel region are concave in a direction perpendicular to current flow through the second channel region.

13. The semiconductor device of claim 8, wherein the first channel region has one less second epitaxial layer than the second channel region.

14. The semiconductor device of claim 8, further comprising a dielectric layer over the substrate, the dielectric layer having a first thickness adjacent the first channel region and a second thickness adjacent the second channel region, the first thickness being different than the second thickness.

15. A semiconductor device comprising:

a substrate;

a first transistor comprising a first channel region and a first gate electrode, the first channel region comprising alternating layers of a first epitaxial material and a second epitaxial material, wherein sidewalls of the first epitaxial material in the first channel region have a first shape, wherein the first gate electrode overlies the alternating layers of the first epitaxial material and the second epitaxial material in the first channel region; and

a second transistor comprising a second channel region and a second gate electrode, the second channel region comprising alternating layers of the first epitaxial material and the second epitaxial material, wherein the second gate electrode overlies the alternating layers of the first epitaxial material and the second epitaxial material in the second channel region, wherein sidewalls of the first epitaxial material in the second channel region has a second shape different than the first shape.

16. The semiconductor device of claim 15, wherein the first shape is concave.

17. The semiconductor device of claim 16, wherein the second shape is linear.

18. The semiconductor device of claim 15, wherein the first shape is a “

V”

shape.

19. The semiconductor device of claim 15, wherein the first transistor comprises a first gate dielectric, the first gate dielectric extending from a first sidewall of a bottommost second epitaxial material between the bottommost second epitaxial material and the substrate to a second sidewall of the bottommost second epitaxial material in a direction perpendicular to current flow in the first channel region.

20. The semiconductor device of claim 15, wherein the second transistor has more layers of the second epitaxial material in the second channel region than in the first channel region.