Method of forming a nanosheet transistor

• US 10,535,733 B2
• Filed: 01/11/2018
• Issued: 01/14/2020
• Est. Priority Date: 01/11/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Lee, Choonghyun, Li, Juntao, Xu, Peng
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US15/868,003
• Publication Number:
  US 20190214459A1
• Time in Patent Office: 733 Days
• Field of Search: 257327
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.

Claims

1. A method of forming a nanosheet transistor comprising:

forming a substrate;

forming a first low germanium (Ge) containing layer over the substrate;

forming a first silicon germanium (SiGe) sacrificial nanosheet over the first low Ge containing layer, wherein the first SiGe sacrificial nanosheet has a higher Ge content than the first low Ge containing layer;

forming a second low Ge containing layer on the first SiGe sacrificial nanosheet;

forming a first silicon channel nanosheet on the second low Ge containing layer;

performing a first etch on the first and second low Ge containing layers and the SiGe sacrificial nanosheet to form first recesses in the SiGe sacrificial nanosheet;

deposing a layer of germanium oxide over the substrate and the first silicon channel nanosheet and on sides of the first and second low Ge containing layers and sides of the first SiGe sacrificial nanosheet to form an intermediate gate stack;

annealing the intermediate gate stack to produce a silicon oxide where the layer of germanium oxide contacts the first SiGe sacrificial nanosheet in the first recesses;

removing the layer of germanium oxide;

performing a second etch on the first and second low Ge containing layers;

removing the silicon oxide to form recesses between the substrate and first silicon channel nanosheet;

forming spacers in the uniform recesses to create a modified sacrificial gate stack;

forming a source on side of the modified sacrificial gate stack and a drain on another side of the modified sacrificial gate stack;

removing the first and second low Ge containing layers and the SiGe sacrificial nanosheet from the modified sacrificial gate stack; and

forming a final gate stack by depositing a metal in regions formerly occupied by the first and second low Ge containing layers and the SiGe sacrificial nanosheet.

2. The method of claim 1, wherein the concentration of Ge in the first and second low germanium (Ge) containing layers comprises about 10%.

3. The method of claim 1, wherein the concentration of Ge in the SiGe sacrificial nanosheet comprises about 40%.

4. The method of claim 1, further comprising:

forming a third low Ge containing layer on the first silicon channel nanosheet;

forming a second (SiGe) sacrificial nanosheet over the third low Ge containing layer;

forming a fourth low Ge containing layer on the second SiGe sacrificial nanosheet;

forming a second silicon channel nanosheet on the fourth low Ge containing layer;

forming a fifth low Ge containing layer on the second silicon channel nanosheet;

forming a third SiGe sacrificial nanosheet over the fifth low Ge containing layer;

forming a sixth low Ge containing layer on the third SiGe sacrificial nanosheet; and

forming a third silicon channel nanosheet on the sixth low Ge containing layer.

5. The method of claim 4, further comprising:

forming a dummy gate stack on top and sidewalls of the nanosheet stack; and

forming a dielectric spacer spacers on sides of the dummy gate;

wherein the intermediate gate stack includes the dummy gate and the dielectric spacers.

6. The method of claim 1, wherein the intermediate gate stack is annealed.

7. The method of claim 1, wherein water is used to remove the layer of germanium oxide.

8. The method of claim 1, wherein the first and second etches are time etches.

9. The method of claim 8, wherein the first and second etches are performed with an aqueous solution containing the mixture of ammonia and hydrogen peroxide.