Selective silicon growth for gapfill improvement

• US 10,535,751 B2
• Filed: 05/30/2018
• Issued: 01/14/2020
• Est. Priority Date: 05/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, De-Wei, Chen, Chien-Hao, Liang, Pin-Ju, Yang, I-chen
• Primary Examiner(s): Bachner, Robert G
• Assistant Examiner(s): Reida, Molly K
• Application Number:
  US15/992,357
• Publication Number:
  US 20190371914A1
• Time in Patent Office: 594 Days
• CPC Class Codes: C23C 16/045 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: C23C 16/45504 Laminar flow
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film.

Claims

1. A method for semiconductor process, the method comprising:

forming fins on a substrate, sidewalls of the fins and a bottom surface defining a trench therebetween;

filling the trench with a gate layer comprising performing a cyclic deposition-treatment process on the substrate in a processing chamber, the cyclic deposition-treatment process comprising;

forming a first portion of the gate layer in the trench and along the sidewalls of the fins;

forming respective passivation layers on the first portion of the gate layer formed at respective top portions of the fins; and

forming a second portion of the gate layer on the first portion of the gate layer not covered by the passivation layer; and

after the trenches are filled with the gate layer, patterning the gate layer to form a gate structure over the fins.

2. The method of claim 1, wherein the gate layer is amorphous silicon.

3. The method of claim 1, wherein the passivation layers are formed by exposing the substrate to a treatment gas comprising a halogen-containing precursor.

4. The method of claim 3, wherein the halogen-containing precursor is a halogen hydride.

5. The method of claim 3, wherein the halogen-containing precursor comprises hydrogen iodide (HI), hydrogen bromide (HBr), hydrogen chloride, or a combination thereof.

6. The method of claim 1, wherein the substrate is at a temperature of 350°

C. or above and a chamber pressure is in a range from 1 Torr to 80 Torr while exposing the substrate to a treatment gas.

7. The method of claim 1, wherein the processing chamber is a low-pressure chemical vapor deposition (LPCVD) chamber.

8. A method for semiconductor process, the method comprising:

forming fins on a substrate, sidewalls of the fins and a bottom surface defining a trench therebetween;

forming a dummy gate layer over the fins, comprising;

introducing a deposition gas, in a first deposition process, into a processing chamber in which the substrate is disposed to form a first portion of the dummy gate layer in the trench and over the fins;

after introducing the deposition gas in the first deposition process, introducing a treatment gas into the processing chamber at a temperature of 350°

C. or above to form respective passivation layers on the first portion of the dummy gate layer at respective top portions of the fins;

after introducing the treatment gas, introducing the deposition gas, in a second deposition process, into the processing chamber to form a second portion of the dummy gate layer on the first portion of the dummy gate layer not covered by the respective passivation layers, the dummy gate layer formed at the respective top portions of the fins having a first thickness T1, and the dummy gate layer at a bottom of the trench having a second thickness T2; and

after introducing the deposition gas in the second deposition process, switching the deposition gas to the treatment gas when the ratio of T1 to T2 reaches 30;

1 or above; and

after forming the dummy gate layer, patterning the dummy gate layer to form a gate structure over the fins.

9. The method of claim 8, wherein the dummy gate layer is amorphous silicon.

10. The method of claim 8, wherein the treatment gas comprises a halogen hydride.

11. The method of claim 8, wherein the halogen-containing precursor comprises hydrogen iodide (HI), hydrogen bromide (HBr), or a combination thereof.

12. The method of claim 8, wherein the processing chamber is a low-pressure chemical vapor deposition (LPCVD) chamber.

13. A method for semiconductor process, the method comprising:

forming a first fin and a second fin on a substrate, a first sidewall of the first fin and a second sidewall of the second fin forming sidewalls of a trench; and

performing a cyclic deposition-treatment process to form a layer in the trench, the cyclic deposition-treatment process comprising;

forming a first portion of the layer along a bottom and the sidewalls of the trench, the layer extending over the first fin and the second fin; and

forming a first passivation layer on the first portion of the layer on an upper surface of the first fin and the first portion of the layer on an upper surface of the second fin, wherein the first portion of the first layer along a bottom of the trench is free of the first passivation layer; and

forming a second portion of the layer along the bottom and the sidewalls of the trench, the second portion of the layer extending over the first passivation layer.

14. The method of claim 13, further comprising:

forming a second passivation layer on the second portion of the layer on the upper surface of the first fin and the second portion of the layer on the upper surface of the second fin, wherein the second portion of the first layer along the bottom of the trench is free of the second passivation layer.

15. The method of claim 13, wherein the layer comprises amorphous silicon or polysilicon.

16. The method of claim 15, wherein forming the first passivation layer comprises exposing the layer to a halogen-containing precursor.

17. The method of claim 16, wherein the halogen-containing precursor comprises hydrogen bromide (HBr), hydrogen iodide (HI), or hydrogen chloride (HCl).

18. The method of claim 13, wherein a ratio of a first vertical height of the first passivation layer to a second vertical height of a sidewall of the first portion of the layer is in a range from 1:

3 to 1;

10.

19. The method of claim 13, wherein forming the first portion of the layer comprises conformally depositing the first portion of the layer.

20. The method of claim 13, wherein the forming the first portion of the layer and forming the first passivation layer is performed in a same processing chamber, and further comprising purging the same processing chamber after forming the first portion and prior to forming the first passivation layer.