Gate structure of field effect transistor with footing

• US 10,535,758 B2
• Filed: 06/04/2019
• Issued: 01/14/2020
• Est. Priority Date: 02/14/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Chen, Chang-Yin, Lin, Jr-Jung, Lin, Chih-Han, Chang, Yung Jung
• Primary Examiner(s): Carter, Michael
• Application Number:
  US16/430,834
• Publication Number:
  US 20190319120A1
• Time in Patent Office: 224 Days
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Claims

1. A field effect transistor (FET) structure, comprising:

a first substrate having a surface, the first substrate including;

a first semiconductor structure comprising;

a channel region, and

a source region and a drain region formed on opposite ends of the channel region, respectively;

a gate structure comprising;

a central region formed over the surface of the first substrate and at least wrapping around three sides of the channel region, and footing regions formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure;

wherein the central region includes a gate dielectric, a work function metal layer and a fill metal, wherein the work function metal layer extends to the footing regions, and the fill metal does not extend to the footing regions; and

an interfacial layer formed between the first semiconductor structure and the gate structure, wherein the interfacial layer laterally protrudes from each end of the footing regions.

2. The FET structure of claim 1, wherein each footing region is tapered towards the central region from a first end of the footing region to a second end of the footing region, and the first end of the footing region is closer to the first semiconductor structure than the second end of the footing region.

3. The FET structure of claim 1, wherein the gate dielectric extends to the footing regions.

4. The FET structure of claim 1, wherein each of the source region and the drain region comprises or is in contact with a stressor material that has a lattice constant different from that of a material of the channel region.

5. The FET structure of claim 1,

wherein the first semiconductor structure comprises a fin structure.

6. The FET structure of claim 5, further comprising:

a gate spacer formed over a side wall of the gate structure, wherein the side wall of the gate structure traverses the first semiconductor structure; and

a fin spacer formed over a side wall of an exposed portion of the first semiconductor structure on a side of the gate structure,

wherein the gate spacer and the fin spacer form an L-shaped cross-section , the L-shaped cross-section is substantially parallel to the surface of the first substrate and the L-shaped cross-section has an indented corner that abuts one of the footing regions.

7. The FET structure of claim 6, further comprising:

a source extension region formed between the channel region and the source region, wherein the source extension region is more lightly doped than the source region; and

a drain extension region formed between the channel region and the drain region, wherein the drain extension region is more lightly doped than the drain region.

8. The FET structure of claim 1, wherein the first substrate further comprises:

a second substrate; and

an insulator layer over the second substrate,

wherein the first semiconductor structure is configured over the insulator layer, and

the gate structure is formed over the channel region.

9. A semiconductor structure, comprising:

a first semiconductor structure;

a gate structure comprising;

a central region formed over the first semiconductor structure, and

footing regions formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure;

wherein the central region includes a gate dielectric, a work function metal layer and a fill metal, wherein the work function metal layer extends to the footing regions, and the fill metal does not extend to the footing regions; and

an interfacial layer, formed between the gate structure and the first semiconductor structure, wherein the interfacial layer laterally protrudes from each end of the footing regions.

10. The semiconductor structure of claim 9, wherein each footing region is tapered toward the central region from a first end of the footing region to a second end of the footing region, and the first end of the footing region is closer to the first semiconductor structure than the second end of the footing region.

11. The semiconductor structure of claim 9, wherein the gate dielectric extends to the footing regions.

12. The semiconductor structure of claim 9,

wherein the first semiconductor structure comprises a fin structure.

13. The semiconductor structure of claim 9, further comprising:

a second substrate; and

an insulator layer over the second substrate,

wherein the first semiconductor structure is configured over the insulator layer, and

the gate structure is formed over a channel region of the first semiconductor structure.

14. A semiconductor structure, comprising:

a first semiconductor structure comprising;

a channel region, and

a source region and a drain region formed on opposite ends of the channel region, respectively;

a gate structure comprising;

a gate dielectric;

a work function metal layer; and

a fill metal;

wherein a central region of the gate structure is formed over the first semiconductor structure, and a portion of the gate dielectric and a portion of the work function metal layer form footing regions of the gate structure on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure,

wherein each footing region is tapered towards the central region from a first end of the footing region to a second end of the footing region, and the first end of the footing region is closer to the first semiconductor structure than the second end of the footing region; and

an interfacial layer formed between the first semiconductor structure and the gate structure, wherein the interfacial layer laterally protrudes from each end of the footing regions.

15. The semiconductor structure of claim 14, wherein each of the source region and the drain region comprises or is in contact with a stressor material that has a lattice constant different from that of a material of the channel region.

16. The semiconductor structure of claim 14, further comprising:

a substrate that comprises a surface,

wherein the first semiconductor structure comprises a fin structure, and the fin structure protrudes from the surface of the substrate; and

the gate structure wraps around at least three sides of the channel region.

17. The semiconductor structure of claim 16, further comprising:

a gate spacer formed over a side wall of the gate structure, wherein the side wall of the gate structure traverses the first semiconductor structure; and

a fin spacer formed over a side wall of an exposed portion of the first semiconductor structure on a side of the gate structure,

wherein the gate spacer and the fin spacer form an L-shaped cross-section , the L-shaped cross-section is substantially parallel to the surface of the substrate and the L-shaped cross-section has an indented corner that abuts one of the footing regions.

18. The semiconductor structure of claim 17, further comprising:

a source extension region formed between the channel region and the source region, wherein the source extension region is more lightly doped than the source region; and

a drain extension region formed between the channel region and the drain region, wherein the drain extension region is more lightly doped than the drain region.

19. The semiconductor structure of claim 14, further comprising:

a second substrate; and

an insulator layer over the second substrate,

wherein the first semiconductor structure is configured over the insulator layer, and

the gate structure is formed over the channel region.

20. The semiconductor structure of claim 14, further comprising:

a source extension region formed between the channel region and the source region, wherein the source extension region is more lightly doped than the source region; and

a drain extension region formed between the channel region and the drain region, wherein the drain extension region is more lightly doped than the drain region.