Power semiconductor device

• US 10,535,765 B2
• Filed: 08/31/2018
• Issued: 01/14/2020
• Est. Priority Date: 04/18/2018
• Status: Active Grant

• Current Assignee: uPI Semiconductor Corporation (ASUSTek Computer, Inc.)
• Original Assignee: uPI Semiconductor Corporation (ASUSTek Computer, Inc.)
• Inventors: Chen, Chin-Fu
• Primary Examiner(s): Miller, Jami Valentine
• Application Number:
  US16/118,449
• Publication Number:
  US 20190326430A1
• Time in Patent Office: 501 Days
• Field of Search: 257288
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device including a substrate having an active region and a terminal region is provided. The terminal region surrounds the active region. A first epitaxial layer is disposed on the substrate in the active region and the terminal region. A second epitaxial layer is disposed on the first epitaxial layer. The second epitaxial layer includes a first termination trench, a second termination trench, and a third termination trench. The first termination trench is disposed in the terminal region and is adjacent to the active region. The second termination trench is disposed in the terminal region. The third termination trench is disposed in the terminal region. The second termination trench is located between the first termination trench and the third termination trench. The third termination trench has a third electrode electrically connected to a drain.

Claims

1. A power semiconductor device, comprising:

a substrate, having an active region and a terminal region, the terminal region surrounding the active region;

a first epitaxial layer, disposed on the substrate in the active region and the terminal region; and

a second epitaxial layer, disposed on the first epitaxial layer, wherein a doping concentration of the second epitaxial layer is greater than a doping concentration of the first epitaxial layer, wherein the second epitaxial layer comprises;

a first termination trench, disposed in the terminal region and adjacent to the active region;

a second termination trench, disposed in the terminal region; and

a third termination trench, disposed in the terminal region, wherein the second termination trench is located between the first termination trench and the third termination trench, and the third termination trench has a third electrode electrically connected to a drain.

2. The power semiconductor device as claimed in claim 1, wherein the first termination trench has a first electrode being electrically connected to a source.

3. The power semiconductor device as claimed in claim 1, wherein the second termination trench has a second electrode being electrically connected to a source or electrically floating.

4. The power semiconductor device as claimed in claim 1, wherein a distance between the first termination trench and the second termination trench is greater than a distance between the second termination trench and the third termination trench.

5. The power semiconductor device as claimed in claim 1, further comprising a plurality of active trenches, disposed in the second epitaxial layer in the active region, extending in a first direction, and alternately arranged along a second direction, wherein the first direction is different from the second direction.

6. The power semiconductor device as claimed in claim 5, wherein the first termination trench and the active trenches are separated from each other.

7. The power semiconductor device as claimed in claim 5, wherein the first termination trench and the active trenches are connected to each other.

8. The power semiconductor device as claimed in claim 1, wherein the first termination trench, the second termination trench, and the third termination trench are separated from each other.

9. The power semiconductor device as claimed in claim 1, wherein the first termination trench, the second termination trench, and the third termination trench further extend into the first epitaxial layer.