Semiconductor device including an epitaxial layer wrapping around the nanowires

• US 10,535,780 B2
• Filed: 05/08/2017
• Issued: 01/14/2020
• Est. Priority Date: 05/08/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Van Dal, Mark, Doornbos, Gerben
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/588,830
• Publication Number:
  US 20180323312A1
• Time in Patent Office: 981 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A multi-stack nanowire device includes a plurality of fins. Each of the fins has a multi-layer stack comprising a first nanowire and a second nanowire. A first portion of the first nanowire and second nanowire are doped to form source and drain regions. A second portion of the first nanowire and second nanowire is channel regions between the source and drain regions. An epitaxial layer wraps around the second portion of first nanowire and second nanowire. A gate is disposed over the second portion of the first nanowire and second nanowire. The epitaxial layer is interposed in between the first nanowire and the second nanowire over the channel region.

Claims

1. A semiconductor device comprising:

a multi-layer stack comprising a first nanowire and a second nanowire, wherein the first nanowire comprises first source/drain regions and a first channel region between the first source/drain regions, and the second nanowire comprises second source/drain regions and a second channel region between the second source/drain regions;

an epitaxial layer wrapping around the first channel region of the first nanowire and the second channel region of the second nanowire, wherein the epitaxial layer has a portion between the first nanowire and the second nanowire and an inner surface in contact with the first channel region, and the epitaxial layer is in direct contact with an entirety of a topmost surface of the first channel region of the first nanowire; and

a gate dielectric layer in contact with an outer surface of the epitaxial layer opposite to the inner surface of the epitaxial layer, wherein an interface between the gate dielectric layer and the outer surface of epitaxial layer is non-parallel with a sidewall of the first nanowire.

2. The semiconductor device of claim 1, wherein the epitaxial layer has a zigzag contour.

3. The semiconductor device of claim 1, wherein the epitaxial layer includes Ge, Si, SiGe or a combination thereof.

4. The semiconductor device of claim 1, wherein the interface between the gate dielectric layer and the outer surface of the epitaxial layer is a <

111>

plane.

5. The semiconductor device of claim 1, further comprising a work function metal layer over the gate dielectric layer.

6. The semiconductor device of claim 1, wherein the interface between the gate dielectric layer and the outer surface of the epitaxial layer is non-parallel with a top surface of the first nanowire.

7. The semiconductor device of claim 1, wherein the interface between the gate dielectric layer and the outer surface of the epitaxial layer is non-parallel with a bottom surface of the first nanowire.

8. The semiconductor device of claim 1, wherein the interface between the gate dielectric layer and the outer surface of the epitaxial layer is non-parallel with a sidewall of the second nanowire.

9. The semiconductor device of claim 1, wherein when viewed in a cross section taken along a direction parallel with a height of the first nanowire, the epitaxial layer completely surrounds the first channel region of the first nanowire.

10. A semiconductor device comprising:

a plurality of nanowires each having source/drain regions and a channel region between the source/drain regions;

a plurality of epitaxial layers respectively wrapping and directly contacting the channel regions of the nanowires, wherein the epitaxial layers are spaced apart, and an outer surface of at least one of the epitaxial layers is not conformal to an outer surface of at least one of the nanowires wrapped by the at least one of the epitaxial layers; and

a gate electrode disposed around the epitaxial layers.

11. The semiconductor device of claim 10, wherein the outer surface of the at least one of the epitaxial layers has a diamond contour.

12. The semiconductor device of claim 10, wherein the epitaxial layers include Ge, Si, SiGe or a combination thereof.

13. The semiconductor device of claim 10, further comprising a gate dielectric layer in contact with the epitaxial layers.

14. The semiconductor device of claim 13, wherein an interface between the gate dielectric layer and at least one of the epitaxial layers is a <

111>

plane.

15. The semiconductor device of claim 10, further comprising a high-k gate dielectric layer wrapping around the epitaxial layers.

16. The semiconductor device of claim 15, wherein the gate electrode comprises a work function metal layer over the high-k gate dielectric layer.

17. A semiconductor device, comprising:

a plurality of nanowires each having source/drain regions and a channel region between the source/drain regions;

a plurality of epitaxial layers, each of which wraps and directly contacts a respective one of the channel regions of the nanowires, wherein each of the epitaxial layers comprises a tip and facets meeting at the tip, and the tips of an adjacent pair of the epitaxial layers are sandwiched between the adjacent pair of the epitaxy layers and are in contact with each other;

a gate dielectric layer in contact with the tips of the adjacent pair of the epitaxial layers; and

a gate electrode disposed around the gate dielectric layer and the epitaxial layers.

18. The semiconductor device of claim 17, wherein the gate dielectric layer is in contact with the facets of the epitaxial layers.

19. The semiconductor device of claim 17, wherein an interface between the gate dielectric layer and one of the epitaxial layers is a <

111>

plane.

20. The semiconductor device of claim 19, wherein a sidewall of one of the nanowires is non-parallel with the <

111>

plane.