Comparator architecture and related methods
First Claim
1. A circuit comprising:
- a first stage configured to receive an input voltage and a reference voltage, the first stage comprising a reference transistor pair and a clamp transistor, wherein;
the reference voltage is coupled to the reference transistor pair;
the reference transistor pair is coupled to ground;
the reference transistor pair comprises at a common drain a drain-gate node having a drain-gate voltage; and
a source of the clamp transistor is coupled to a high-gain node, a gate of the clamp transistor is coupled to a clamp voltage, anda second stage coupled to the high-gain node and configured to generate an output voltage based on a difference between the input voltage and the reference voltage, the second stage comprising a resistor and an inverter transistor pair, wherein;
gates of the inverter transistor pair are coupled to the high-gain node of the first stage; and
the resistor couples the high-gain node of the first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of the first stage.
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Abstract
A system is disclosed. The system includes a first stage configured to receive VIN and VREF, the first stage including an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes at a common drain a high-gain node having a voltage VHGN. The system further include a second stage coupled to the high-gain node and configured to generate VOUT based on a difference between VIN and VREF, the second stage comprising a resistor and an inverter transistor pair, wherein the gates of the inverter transistor pair are coupled to the high-gain node of the first stage and the resistor couples the high-gain node of first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of first stage.
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Citations
30 Claims
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1. A circuit comprising:
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a first stage configured to receive an input voltage and a reference voltage, the first stage comprising a reference transistor pair and a clamp transistor, wherein; the reference voltage is coupled to the reference transistor pair; the reference transistor pair is coupled to ground; the reference transistor pair comprises at a common drain a drain-gate node having a drain-gate voltage; and a source of the clamp transistor is coupled to a high-gain node, a gate of the clamp transistor is coupled to a clamp voltage, and a second stage coupled to the high-gain node and configured to generate an output voltage based on a difference between the input voltage and the reference voltage, the second stage comprising a resistor and an inverter transistor pair, wherein; gates of the inverter transistor pair are coupled to the high-gain node of the first stage; and the resistor couples the high-gain node of the first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of the first stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method, comprising:
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receiving, at a first stage comprising a reference transistor pair, a clamp transistor, an input voltage and a reference voltage, wherein; the reference voltage is coupled to the reference transistor pair; the reference transistor pair is coupled to ground; the reference transistor pair comprises at a common drain a drain-gate node having a drain-gate voltage; and a source of the clamp transistor is coupled to a high-gain node, a gate of the clamp transistor is coupled to a clamp voltage; and receiving, at a second stage comprising a resistor and an inverter transistor pair, ae high-gain node voltage, wherein; gates of the inverter transistor pair are coupled to the high-gain node of the first stage; and the resistor couples the high-gain node of the first stage to a common drain of the inverter transistor pair; providing or drawing current to or from the high-gain node of the first stage; and generating an output voltage based on a difference between the input voltage and the reference voltage. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A circuit, comprising:
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means for receiving an input voltage and a reference voltage, wherein the means for receiving comprises means for providing a drain-gate voltage and means for clamping a high-gain node; means for providing or drawing current to or from the high-gain node of a first stage; and means for generating an output voltage based on a difference between the input voltage and the reference voltage. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification