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Comparator architecture and related methods

  • US 10,536,143 B1
  • Filed: 09/13/2019
  • Issued: 01/14/2020
  • Est. Priority Date: 05/31/2018
  • Status: Active Grant
First Claim
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1. A circuit comprising:

  • a first stage configured to receive an input voltage and a reference voltage, the first stage comprising a reference transistor pair and a clamp transistor, wherein;

    the reference voltage is coupled to the reference transistor pair;

    the reference transistor pair is coupled to ground;

    the reference transistor pair comprises at a common drain a drain-gate node having a drain-gate voltage; and

    a source of the clamp transistor is coupled to a high-gain node, a gate of the clamp transistor is coupled to a clamp voltage, anda second stage coupled to the high-gain node and configured to generate an output voltage based on a difference between the input voltage and the reference voltage, the second stage comprising a resistor and an inverter transistor pair, wherein;

    gates of the inverter transistor pair are coupled to the high-gain node of the first stage; and

    the resistor couples the high-gain node of the first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of the first stage.

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